HYB25DC512800B Datasheet, PDF (17/35 Pages) Qimonda AG – 512-Mbit Double-Data-Rate SDRAM

Internet Data Sheet
HYB25DC512[80/16]0B[E/F]
Double-Data-Rate SDRAM
8) Internal refresh counter controls row and bank addressing; all inputs and I/Os are “Don’t Care” except for CKE.
9) BA0, BA1 select either the Base or the Extended Mode Register (BA0 = 0, BA1 = 0 selects Mode Register; BA0 = 1, BA1 = 0 selects
Extended Mode Register; other combinations of BA0-BA1 are reserved; A0-A12 provide the op-code to be written to the selected Mode
Register).
Name (Function)
Write Enable
Write Inhibit
1) Used to mask write data; provided coincident with the corresponding data.
TABLE 13
Truth Table 1b: DM Operation
DM
DQs Note
L
Valid ¹⁾
H
X
1)
Current State CKE n-1 CKEn
Command n
TABLE 14
Truth Table 2: Clock Enable (CKE)
Action n
Note
Previous Current
Cycle
Cycle
Self Refresh L
Self Refresh L
L
X
H
Deselect or NOP
Maintain Self-Refresh
1)
Exit Self-Refresh
2)
Power Down L
L
X
Maintain Power-Down
—
Power Down L
H
Deselect or NOP
Exit Power-Down
—
All Banks Idle H
L
Deselect or NOP
Precharge Power-Down Entry —
All Banks Idle H
L
AUTO REFRESH
Self Refresh Entry
—
Bank(s) Active H
L
Deselect or NOP
Active Power-Down Entry
—
H
H
See Table 15
—
—
1) V_REF must be maintained during Self Refresh operation
2) Deselect or NOP commands should be issued on any clock edges occurring during the Self Refresh Exit (t_XSNR) period. A minimum of 200
clock cycles are needed before applying a read command to allow the DLL to lock to the input clock.
1. CKEn is the logic state of CKE at clock edge n: CKE n-1 was the state of CKE at the previous clock edge.
2. Current state is the state of the DDR SDRAM immediately prior to clock edge n.
3. COMMAND n is the command registered at clock edge n, and ACTION n is a result of COMMAND n.
4. All states and sequences not shown are illegal or reserved.
Rev. 1.2, 2007-04
17
04112007-FHBX-O8HD