HYS72T64400HFD Datasheet, PDF (6/42 Pages) Qimonda AG – 240-Pin Fully-Buffered DDR2 SDRAM Modules

Internet Data Sheet
HYS72T[64/128/256]4[00/20]HFD–[3S/3.7]–A
2
Pin Configuration
The pin configuration of the DDR2 SDRAM DIMM is listed by function in Table 5 (240 pins). The abbreviations used in columns
Pin and Buffer Type are explained in Table 6 and Table 7 respectively. The pin numbering is depicted in Figure 1.
Pin#
Clock Signals
228
229
Control Signals
17
Northbound
22
25
28
31
34
37
51
54
57
60
63
66
48
40
23
26
29
32
35
38
52
55
58
61
64
Name
Pin
Type
SCK
I
SCK
I
RESET I
PN0
O
PN1
O
PN2
O
PN3
O
PN4
O
PN5
O
PN6
O
PN7
O
PN8
O
PN9
O
PN10
O
PN11
O
PN12
O
PN13
O
PN0
O
PN1
O
PN2
O
PN3
O
PN4
O
PN5
O
PN6
O
PN7
O
PN8
O
PN9
O
PN10
O
Buffer
Type
TABLE 5
Pin Configuration of FB-DIMM
Function
HSDL_15
HSDL_15
System Clock Input, positive line
System Clock Input, negative line
LV-CMOS AMB reset signal
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
Primary Northbound Data, positive lines
Rev. 1.2, 2006-11
6
03292006-GUME-ERC3