HYS72T64400HFD Datasheet, PDF (19/42 Pages) Qimonda AG – 240-Pin Fully-Buffered DDR2 SDRAM Modules

Internet Data Sheet
HYS72T[64/128/256]4[00/20]HFD–[3S/3.7]–A
5
Current Spec. and Conditions
The following table provides an overview of the measurement conditions.
Parameter
Idle Current, single or last DIMM
L0 state, idle (0 BW)
Primary channel enabled, Secondary channel disabled
CKE high. Command and address lines stable.
DRAM clock active
Idle Current, first DIMM
L0 state, idle (0 BW)
Primary and Secondary channels enabled.
CKE high. Command and address lines stable.
DRAM clock active
Active Power
L0 state
50% DRAM BW, 67% read, 33% write.
Primary and Secondary channels enabled.
DRAM clock active, CKE high.
Active Power, data pass through
L0 state
50% DRAM BW to downstream DIMM, 67% read, 33% write.
Primary and Secondary channels enabled.
CKE high. Command and address lines stable.
DRAM clock active.
Training
Primary and Secondary channels enabled.
100% toggle on all channels lanes.
DRAMs idle (0 BW).
CKE high. Command and address lines stable.
DRAM clock active.
IBIST
Over all IBIST modes
DRAM Idle (0 BW)
Primary channel Enabled
Secondary channel Enabled
CKE high. Command and Address lines stable
DRAM clock active
TABLE 13
I_DD Measurement Conditions
Symbol
I_{CC_Idle_0}
I_{DD_Idle_0}
I_{CC_Idle_1}
I_{DD_Idle_1}
I_{CC_Active_1}
I_{DD_Active_1}
I_{CC_Active_2}
I_{DD_Active_2}
I_{CC_Training}
I_{DD_Training}
I_{CC_IBIST}
I_{DD_IBIST}
Rev. 1.2, 2006-11
19
03292006-GUME-ERC3