HYS72T64400HFD Datasheet, PDF (31/42 Pages) Qimonda AG – 240-Pin Fully-Buffered DDR2 SDRAM Modules

Product Type
Internet Data Sheet
HYS72T[64/128/256]4[00/20]HFD–[3S/3.7]–A
Organization
512MB
1 GByte
2 GByte
×72
×72
×72
1 Rank (×8)
2 Ranks (×8)
2 Ranks (×4)
Label Code
PC2–4200F–444 PC2–4200F–444 PC2–4200F–444
JEDEC SPD Revision
Rev. 1.1
Rev. 1.1
Rev. 1.1
Byte# Description
HEX
23
t_RAS.MIN (min. Active to Precharge Time)
B4
24
t_RC.MIN (min. Active to Active / Refresh Time)
F0
25
t_RFC.MIN LSB (min. Refresh Recovery Time Delay)
A4
26
t_RFC.MIN MSB (min. Refresh Recovery Time Delay)
01
27
t_WTR.MIN (min. Internal Write to Read Cmd Delay)
1E
28
t_RTP.MIN (min. Internal Read to Precharge Cmd Delay) 1E
29
Burst Lengths Supported
03
30
Terminations Supported
07
31
Drive Strength Supported
01
32
t_REFI (avg. SDRAM Refresh Period)
C2
33
T_CASE.MAX Delta / ∆T_4R4W Delta
51
34
Psi(T-A) DRAM
78
35
∆T₀ (DT0) DRAM
3C
36
∆T_2Q (DT2Q) DRAM
22
37
∆T_2P (DT2P) DRAM
1E
38
∆T_3N (DT3N) DRAM
1E
39
∆T_4R (DT4R) / ∆T_4R4W Sign (DT4R4W) DRAM
34
40
∆T_5B (DT5B) DRAM
1E
41
∆T₇ (DT7) DRAM
20
42 - 78 Not used
00
79
FBDIMM ODT Values
01
80
Not used
00
81
Channel Protocols Supported LSB
02
82
Channel Protocols Supported MSB
00
83
Back-to-Back Access Turnaround Time
00
84
AMB Read Access Delay for DDR2-800
36
HEX
B4
F0
A4
01
1E
1E
03
07
01
C2
51
78
3C
22
1E
1E
34
1E
20
00
22
00
02
00
00
36
HEX
B4
F0
A4
01
1E
1E
03
07
01
C2
51
78
3C
22
1E
1E
34
1E
20
00
22
00
02
00
00
36
Rev. 1.2, 2006-11
31
03292006-GUME-ERC3