HYS72T64400HFD Datasheet, PDF (30/42 Pages) Qimonda AG – 240-Pin Fully-Buffered DDR2 SDRAM Modules

Product Type
Internet Data Sheet
HYS72T[64/128/256]4[00/20]HFD–[3S/3.7]–A
TABLE 17
PC2–4200F–444
Organization
Label Code
JEDEC SPD Revision
Byte#
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
Description
SPD Size CRC / Total / Used
SPD Revision
Key Byte / DRAM Device Type
Voltage Level of this Assembly
SDRAM Addressing
Module Physical Attributes
Module Type
Module Organization
Fine Timebase (FTB) Dividend and Divisor
Medium Timebase (MTB) Dividend
Medium Timebase (MTB) Divisor
t_CK.MIN (min. SDRAM Cycle Time)
t_CK.MAX (max. SDRAM Cycle Time)
CAS Latencies Supported
t_CAS.MIN (min. CAS Latency Time)
Write Recovery Values Supported (WR)
t_WR.MIN (Write Recovery Time)
Write Latency Times Supported
Additive Latency Times Supported
t_RCD.MIN (min. RAS# to CAS# Delay)
t_RRD.MIN (min. Row Active to Row Active Delay)
t_RP.MIN (min. Row Precharge Time)
t_RAS and t_RC Extension
512MB
1 GByte
2 GByte
×72
×72
×72
1 Rank (×8)
2 Ranks (×8)
2 Ranks (×4)
PC2–4200F–444 PC2–4200F–444 PC2–4200F–444
Rev. 1.1
Rev. 1.1
Rev. 1.1
HEX
92
11
09
12
44
23
07
09
00
01
04
0F
20
33
3C
32
3C
72
50
3C
1E
3C
00
HEX
92
11
09
12
44
23
07
11
00
01
04
0F
20
33
3C
32
3C
72
50
3C
1E
3C
00
HEX
92
11
09
12
48
23
07
10
00
01
04
0F
20
33
3C
32
3C
72
50
3C
1E
3C
00
Rev. 1.2, 2006-11
30
03292006-GUME-ERC3