HYS72T64400HFD Datasheet, PDF (17/42 Pages) Qimonda AG – 240-Pin Fully-Buffered DDR2 SDRAM Modules

Internet Data Sheet
HYS72T[64/128/256]4[00/20]HFD–[3S/3.7]–A
Parameter
Symbol
TABLE 10
Supply Voltage Levels and DC Operating Conditions
Limit Values
Unit Note
Min.
Nom.
Max.
AMB Supply Voltage
V_CC
1.455
1.5
1.575
V
DRAM Supply Voltage
V_DD
1.7
1.8
1.9
V
Termination Voltage
V_TT
0.48 × V_DD
0.50 × V_DD
0.52 × V_DD
V
EEPROM Supply Voltage
V_DDSPD
3.0
3.3
3.6
V
DC Input Logic High(SPD)
V_IH(DC)
2.1
—
V_DDSPD
V
1)
DC Input Logic Low(SPD)
V_IL(DC)
—
—
0.8
V
1)
DC Input Logic High(RESET)
V_IH(DC)
1.0
—
—
V
2)
DC Input Logic Low(RESET)
V_IL(DC)
—
—
+0.5
V
1)
Leakage Current (RESET)
I_L
–90
—
+90
µΑ
2)
Leakage Current (Link)
I_L
–5
—
+5
µΑ
3)
1) applies for SMB and SPD Bus Signals.
2) applies for AMB CMOS Signal RESET.
3) for all other AMB related DC parameters, please refer to the High Speed Differential Link Interface Specifications.
TABLE 11
Timing Parameters
Parameter
Symbol
Min.
Typ.
Max.
Units Note
EI Assertion Pass-Thru Timing
t_{EI Propagate}t
—
—
EI Deassertion Pass-Thru Timing
t_EID
—
—
EI Assertion Duration
t_EI
100
—
FBD Cmd to DDR Clk out that latches Cmd
—
—
8.1
4
Bitlock
—
—
clks
clks
2)
clks
1)2)
ns
3)
FBD Cmd to DDR Write
—
—
TBD
—
ns
DDR Read to FBD (last DIMM)
—
—
5.0
—
ns
4)
Resample Pass-Thru time
—
—
1.075
—
ns
ResynchPass-Thru time
—
—
2.075
—
ns
Bit Lock Interval
t_BitLock
—
—
119
frames ¹⁾
Frame Lock Interval
t_FrameLock
—
—
154
frames ¹⁾
1) Defined in FB-DIMM Architecture and Protocol Spec
2) Clocks defined as core clocks = 2× SCK input
3) @ DDR2-667 - measured from beginning of frame at southbound input to DDR clock output that latches the first command of a frame to
the DRAMs
4) @ DDR2-667 - measured from latest DQS input to AMB to start of matching data frame at northbound FB-DIMM outputs
Rev. 1.2, 2006-11
17
03292006-GUME-ERC3