HYS72T64400HFD Datasheet, PDF (14/42 Pages) Qimonda AG – 240-Pin Fully-Buffered DDR2 SDRAM Modules

Internet Data Sheet
HYS72T[64/128/256]4[00/20]HFD–[3S/3.7]–A
3.3
High-Speed Differential Point-to-Point Link (at 1.5 V)
Interfaces
The Advanced Memory Buffer supports one FB-DIMM
Channel consisting of two bidirectional link interfaces using
highspeed differential point-to-point electrical signaling. The
southbound input link is 10 lanes wide and carries commands
and write data from the host memory controller or the
adjacent DIMM in the host direction. The southbound output
link forwards this same data to the next FB-DIMM. The
northbound input link is 14 lanes wide and carries read return
data or status information from the next FB-DIMM in the chain
back towards the host. The northbound output link forwards
this information back towards the host and multiplexes in any
read return data or status information that is generated
internally. Data and commands sent to the DRAMs travel
southbound on 10 primary differential signal line pairs. Data
received from the DRAMs and status information travel
northbound on 14 primary differential pairs. Data and
commands sent to the adjacent DIMM upstream are repeated
and travel further southbound on 10 secondary differential
pairs. Data and status information received from the adjacent
DIMM upstream travel further northbound on 14 secondary
differential pairs.
3.3.1
DDR2 Channel
The DDR2 channel on the Advanced Memory Buffer supports
direct connection to DDR2 SDRAMs. The DDR2 channel
supports two ranks of eight banks with 16 row/column
request, 64 data, and eight check-bit signals. There are two
copies of address and command signals to support DIMM
routing and electrical requirements. Four transfer bursts are
driven on the data and check-bit lines at 800 MHz.
Propagation delays between read data/check-bit strobe lanes
on a given channel can differ. Each strobe can be calibrated
by hardware state machines using write/read trial and error.
Hardware aligns the read data and check-bits to a single core
clock. The Advanced Memory Buffer provides four copies of
the command clock phase references (CLK[3:0]) and write
data/check-bit strobes (DQSs) for each DRAM nibble.
3.3.2
SMBus Slave Interface
The Advanced Memory Buffer supports an SMBus interface
to allow system access to configuration registers independent
of the FB-DIMM link. The Advanced Memory Buffer will never
be a master on the SMBus, only a slave. Serial SMBus data
transfer is supported at 100 kHz. SMBus access to the
Advanced Memory Buffer may be a requirement to boot and
to set link strength, frequency and other parameters needed
to insure robust configurations. It is also required for
diagnostic support when the link is down. The SMBus
address straps located on the DIMM connector are used by
the unique ID.
3.3.3
Channel Latency
FB-DIMM channel latency is measured from the time a read
request is driven on the FB-DIMM channel pins to the time
when the first 16 bytes (2nd chunk) of read completion data is
sampled by the memory controller. When not using the
Variable Read Latency capability, the latency for a specific
DIMM on a channel is always equal to the latency for any
other DIMM on that channel. However, the latency for each
DIMM in a specific configuration with some number of DIMMs
installed may not be equal to the latency for each FB-DIMM
in a configuration with some different number of DIMMs
installed. As more DIMMs are added to the channel,
additional latency is required to read from each DIMM on the
channel. Because the channel is based on the point-to-point
interconnection of buffer components between DIMMs,
memory requests are required to travel through N-1 buffers
before reaching the Nth buffer. The result is that a 4 DIMM
channel configuration will have greater idle read latency
compared to a 1 DIMM channel configuration. The Variable
Read Latency capability can be used to reduce latency for
DIMMs closer to the host. The idle latencies listed in this
section are representative of what might be achieved in
typical AMB designs. Actual implementations with latencies
less than the values listed will have higher application
performance and vice versa.
Rev. 1.2, 2006-11
14
03292006-GUME-ERC3