HYS72D32300 Datasheet, PDF (6/50 Pages) Qimonda AG – 184-Pin Registered Double Data Rate SDRAM Module

Internet Data Sheet
HYS72D[128/64/32]3xx[G/H]BR–[5/6/7]–C
Registered Double Data Rate SDRAM
2
Pin Configuration
The pin configuration of the Registered DDR SDRAM DIMM
is listed by function in Table 4 (184 pins). The abbreviations
used in columns Pin and Buffer Type are explained in Table 5
and Table 6 respectively. The pin numbering is depicted in
Figure 1.
TABLE 4
Pin Configuration of RDIMM
Pin Name Pin Buffer Function
#
Type Type
Clock Signals
137 CK0 I
138 CK0 I
21 CKE0 I
111 CKE1 I
NC
NC
Control Signals
157 S0
I
158 S1
I
NC
NC
154 RAS I
65 CAS I
63 WE
I
10 RESET I
Address Signals
59 BA0 I
52 BA1 I
48 A0
I
43 A1
I
41 A2
I
130 A3
I
37 A4
I
32 A5
I
SSTL
SSTL
SSTL
SSTL
SSTL
Clock Signal
Complement Clock
Clock Enable Rank 0
Clock Enable Rank 1
Note: 2-rank module
Note: 1-rank module
SSTL Chip Select of Rank 0
SSTL Chip Select of Rank 1
Note: 2-ranks module
—
Note: 1-rank module
SSTL Row Address Strobe
SSTL Column Address Strobe
SSTL Write Enable
LV- Register Reset
CMOS
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
Bank Address Bus 1:0
Address Bus 11:0
Pin Name Pin Buffer Function
#
Type Type
125 A6
I
29 A7
I
122 A8
I
27 A9
I
141 A10
I
AP
I
118 A11
I
115 A12
I
NC
NC
167 A13
I
NC
NC
Data Signals
2 DQ0 I/O
4 DQ1 I/O
6 DQ2 I/O
8 DQ3 I/O
94 DQ4 I/O
95 DQ5 I/O
98 DQ6 I/O
99 DQ7 I/O
12 DQ8 I/O
13 DQ9 I/O
19 DQ10 I/O
20 DQ11 I/O
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
—
SSTL
—
Address Bus 11:0
Address Signal 12
Note: Module based on
256 Mbit or larger
dies
Note: 128 Mbit based
module
Address Signal 13
Note: 1 Gbit based
module
Note: Module based on
512 Mbit or smaller
dies
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
Data Bus 63:0
Rev. 1.32, 2007-03
6
03292006-Q22P-G7TH