HYS72D32300 Datasheet, PDF (20/50 Pages) Qimonda AG – 184-Pin Registered Double Data Rate SDRAM Module

Internet Data Sheet
HYS72D[128/64/32]3xx[G/H]BR–[5/6/7]–C
Registered Double Data Rate SDRAM
Parameter
Symbol –7
DDR266A
Unit Note/Test
Condition ¹⁾
Min.
Max.
Precharge command period
t_RP
20
—
ns
2)3)4)5)
Read preamble
t_RPRE
0.9
1.1
t_CK
2)3)4)5)
Read postamble
t_RPST
0.4
0.6
t_CK
2)3)4)5)
Active bank A to Active bank B command
t_RRD
15
—
ns
2)3)4)5)
Write preamble
t_WPRE
0.25
—
t_CK
2)3)4)5)
Write preamble setup time
t_WPRES
0
—
ns
2)3)4)5)9)
Write postamble
t_WPST
0.4
—
t_CK
2)3)4)5)10)
Write recovery time
t_WR
15
—
ns
2)3)4)5)
Internal write to read command delay
t_WTR
1
—
t_CK
2)3)4)5)
Exit self-refresh to non-read command
t_XSNR
75
—
ns
2)3)4)5)11)
Exit self-refresh to read command
t_XSRD
200
—
t_CK
2)3)4)5)
1) V_DDQ = 2.5 V ± 0.2 V, V_DD = +2.5 V ± 0.2 V ; 0 °C ≤ T_A ≤ 70 °C
2) Input slew rate ≥ 1 V/ns
3) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross: the input reference level for signals
other than CK/CK, is V_REF. CK/CK slew rate are ≥ 1.0 V/ns.
4) Inputs are not recognized as valid until stabilizes.
5) The Output timing reference level, as measured at the timing reference point indicated in AC Characteristics (note 3) is V_TT.
6) t_HZ and t_LZ transitions occur in the same access time windows as valid data transitions. These parameters are not referred to a specific
voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ).
7) Fast slew rate ≥ 1.0 V/ns , slow slew rate ≥ 0.5 V/ns and < 1 V/ns for command/address and CK & CK slew rate > 1.0 V/ns, measured
between V_IH(ac) and V_IL(ac).
8) A maximum of eight Autorefresh commands can be posted to any given DDR SDRAM device.
9) The specific requirement is that DQS be valid (HIGH, LOW, or some point on a valid transition) on or before this CK edge. A valid transition
is defined as monotonic and meeting the input slew rate specifications of the device. When no writes were previously in progress on the
bus, DQS will be transitioning from Hi-Z to logic LOW. If a previous write was in progress, DQS could be HIGH, LOW, or transitioning from
HIGH to LOW at this time, depending on t_DQSS.
10) The maximum limit for this parameter is not a device limit. The device operates with a greater value for this parameter, but system
performance (bus turnaround) degrades accordingly.
11) In all circumstances, t_XSNR can be satisfied using t_XSNR = t_RFC,min + 1 × t_CK
Rev. 1.32, 2007-03
20
03292006-Q22P-G7TH