HYB25D128160C Datasheet, PDF(6/35 Page) Qimonda AG – 128-Mbit Double-Data-Rate SDRAM

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HYB25D128160C Datasheet, PDF (6/35 Pages) Qimonda AG – 128-Mbit Double-Data-Rate SDRAM

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Internet Data Sheet

HYB25D128xxxC[C/E/F/T](L)

128-Mbit Double-Data-Rate SDRAM

2

Pin Configuration

The pin configuration of a DDR SDRAM is listed by function in Table 4 (60 pins). The abbreviations used in the Pin#/Buffer#

column are explained in Table 5 and Table 6 respectively. The pin numbering for FBGA is depicted in Figure 1 and that of the

TSOP package in Figure 2.

Ball#/Pin#

Name

Clock Signals

G2, 45

CK

G3, 46

CK

H3, 44

CKE

Control Signals

H7, 23

RAS

G8, 22

CAS

G7, 21

WE

H8, 24

CS

Address Signals

J8, 26

BA0

J7, 27

BA1

K7, 29

A0

L8, 30

A1

L7, 31

A2

M8, 32

A3

M2, 35

A4

L3, 36

A5

L2, 37

A6

K3, 38

A7

K2, 39

A8

J3, 40

A9

K8, 28

A10

AP

J2, 41

A11

H2, 42

A12

NC

F9, 17

A13

NC

Pin

Type

Buffer

Type

I

SSTL

I

SSTL

I

SSTL

I

SSTL

I

SSTL

I

SSTL

I

SSTL

I

SSTL

I

SSTL

I

SSTL

I

SSTL

I

SSTL

I

SSTL

I

SSTL

I

SSTL

I

SSTL

I

SSTL

I

SSTL

I

SSTL

I

SSTL

I

SSTL

I

SSTL

I

SSTL

NC

â

I

SSTL

NC

â

Function

TABLE 4

Pin Configuration of DDR SDRAM

Clock Signal

Complementary Clock Signal

Clock Enable

Row Address Strobe

Column Address Strobe

Write Enable

Chip Select

Bank Address Bus 2:0

Address Bus 11:0

Address Signal 12

Note: 256 Mbit or larger dies

Note: 128 Mbit or smaller dies

Address Signal 13

Note: 1 Gbit based dies

Note: 512 Mbit or smaller dies

Rev. 1.6, 2007-02

6

03292006-U5AN-6TI1

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