HYB25D128160C Datasheet, PDF (3/35 Pages) Qimonda AG – 128-Mbit Double-Data-Rate SDRAM

Internet Data Sheet
1
Overview
HYB25D128xxxC[C/E/F/T](L)
128-Mbit Double-Data-Rate SDRAM
This chapter contains features and the description.
1.1
Features
• Double data rate architecture: two data transfers per clock cycle
• Bidirectional data strobe (DQS) is transmitted and received with data, to be used in capturing data at the receiver
• DQS is edge-aligned with data for reads and is center-aligned with data for writes
• Differential clock inputs
• Four internal banks for concurrent operation
• Data mask (DM) for write data
• DLL aligns DQ and DQS transitions with CK transitions
• Commands entered on each positive CK edge; data and data mask referenced to both edges of DQS
• Burst Lengths: 2, 4, or 8
• CAS Latency: 2, 2.5, 3
• Auto Precharge option for each burst access
• Auto Refresh and Self Refresh Modes
• RAS-lockout supported t_RAP = t_RCD
• 7.8 µs Maximum Average Periodic Refresh Interval
• 2.5 V (SSTL_2 compatible) I/O
• V_DDQ = 2.5 V ± 0.2 V (DDR266A, DDR333); V_DDQ = 2.6 V ± 0.1 V (DDR400)
• V_DD = 2.5 V ± 0.2 V (DDR266A, DDR333); V_DD = 2.6 V ± 0.1 V (DDR400)
• P(G)-TFBGA-60 package with 3 depopulated rows (8 × 12 mm²)
• P(G)-TSOPII-66 package
• Lead- and halogene-free = green product
Part Number Speed Code
Speed Grade
max. Clock Frequency
Component
Module
@CL3
@CL2.5
@CL2
–5
f_CK3
f_CK2.5
f_CK2
DDR400B
PC3200-3033
200
166
133
–6
DDR333
PC2700–2533
166
166
133
TABLE 1
Performance
–7
Unit
DDR266A
—
PC2100-2033
—
143
133
—
MHz
MHz
MHz
Rev. 1.6, 2007-02
3
03292006-U5AN-6TI1