HYB25D128160C Datasheet, PDF (28/35 Pages) Qimonda AG – 128-Mbit Double-Data-Rate SDRAM

Internet Data Sheet
HYB25D128xxxC[C/E/F/T](L)
128-Mbit Double-Data-Rate SDRAM
11) The specific requirement is that DQS be valid (HIGH, LOW, or some point on a valid transition) on or before this CK edge. A valid transition
is defined as monotonic and meeting the input slew rate specifications of the device. When no writes were previously in progress on the
bus, DQS will be transitioning from Hi-Z to logic LOW. If a previous write was in progress, DQS could be HIGH, LOW, or transitioning from
HIGH to LOW at this time, depending on t_DQSS.
12) The maximum limit for this parameter is not a device limit. The device operates with a greater value for this parameter, but system
performance (bus turnaround) degrades accordingly.
Parameter
DQ output access time from CK/CK
CK high-level width
Clock cycle time
CK low-level width
Auto precharge write recovery + precharge time
DQ and DM input hold time
DQ and DM input pulse width (each input)
DQS output access time from CK/CK
DQS input low (high) pulse width (write cycle)
DQS-DQ skew (DQS and associated DQ signals)
DQS-DQ skew (DQS and associated DQ signals)
Write command to 1^st DQS latching transition
DQ and DM input setup time
DQS falling edge hold time from CK (write cycle)
DQS falling edge to CK setup time (write cycle)
Clock Half Period
Data-out high-impedance time from CK/CK
Address and control input hold time
Control and Addr. input pulse width (each input)
Address and control input setup time
Data-out low-impedance time from CK/CK
Mode register set command cycle time
DQ/DQS output hold time
Symbol
TABLE 23
AC Timing - Absolute Specifications
–7
DDR266A
Unit Note¹⁾/ Test
Condition
t_AC
t_CH
t_CK
t_CL
t_DAL
t_DH
t_DIPW
t_DQSCK
t_DQSL,H
t_DQSQ
t_DQSQ
t_DQSS
t_DS
t_DSH
t_DSS
t_HP
t_HZ
t_IH
Min.
Max.
–0.75
+0.75
0.45
0.55
7.5
12
7.5
12
7.5
12
0.45
0.55
(t_WR/t_CK)+(t_RP/t_CK)
0.5
—
1.75
—
–0.75
+0.75
0.35
—
—
+0.5
—
+0.5
0.75
1.25
0.5
—
0.2
—
0.2
—
min. (t_CL, t_CH)
—
—
+0.75
0.9
—
1.0
1.1
ns
2)3)4)5)
t_CK —
ns CL = 3.0
ns CL = 2.5
ns CL = 2.0
t_CK —
t_CK
6)
ns —
ns —
ns —
t_CK —
ns TFBGA
ns TSOPII
t_CK —
ns —
t_CK —
t_CK —
ns —
ns ⁷⁾
ns fast slew rate
8)
ns slow slew rate
t_IPW
2.2
t_IS
0.9
—
ns ⁹⁾
—
ns fast slew rate
1.0
—
ns slow slew rate
t_LZ
t_MRD
t_QH
–0.75
2
t_HP –t_QHS
+0.75
—
—
ns —
t_CK —
ns —
Rev. 1.6, 2007-02
28
03292006-U5AN-6TI1