HYB25D128160C Datasheet, PDF (24/35 Pages) Qimonda AG – 128-Mbit Double-Data-Rate SDRAM

Internet Data Sheet
HYB25D128xxxC[C/E/F/T](L)
128-Mbit Double-Data-Rate SDRAM
TABLE 19
AC Operating Conditions
Parameter
Symbol
Min.
Values
Max.
Unit Note¹⁾/ Test
Condition
Input High (Logic 1) Voltage, DQ, DQS and DM Signals
V_IH(AC)
V_REF + 0.31 —
V
2)3)
Input Low (Logic 0) Voltage, DQ, DQS and DM Signals
Input Differential Voltage, CK and CK Inputs
Input Closing Point Voltage, CK and CK Inputs
V_IL(AC)
—
V_REF – 0.31 V
—
V_ID(AC)
0.7
V_DDQ + 0.6 V
4)
V_IX(AC)
0.5 × V_DDQ – 0.5 × V_DDQ+ V
5)
0.2
0.2
1) V_DDQ = 2.5 V ± 0.2 V, V_DD = +2.5 V ± 0.2 V (DDR200 - DDR333); V_DDQ = 2.6 V ± 0.1 V, V_DD = +2.6 V ± 0.1 V (DDR400); 0 °C ≤ T_A ≤ 70 °C
2) Input slew rate = 1 V/ns.
3) Inputs are not recognized as valid until V_REF stabilizes.
4) V_ID is the magnitude of the difference between the input level on CK and the input level on CK.
5) The value of V_IX is expected to equal 0.5 × V_DDQ of the transmitting device and must track variations in the DC level of the same.
Parameter
TABLE 20
I_DD Conditions
Symbol
Operating Current: one bank; active/ precharge; t_RC = t_RCMIN; t_CK = t_CKMIN;
I_DD0
DQ, DM, and DQS inputs changing once per clock cycle; address and control inputs changing once every two
clock cycles.
Operating Current: one bank; active/read/precharge; Burst = 4;
I_DD1
Refer to the following page for detailed test conditions.
Precharge Power-Down Standby Current: all banks idle; power-down mode; CKE ≤ V_ILMAX; t_CK = t_CKMIN
Precharge Floating Standby Current: CS ≥ V_IHMIN, all banks idle;
CKE ≥ V_IHMIN; t_CK = t_CKMIN, address and other control inputs changing once per clock cycle, V_IN = V_REF for DQ, DQS
and DM.
I_DD2P
I_DD2F
Precharge Quiet Standby Current:CS ≥ V_IHMIN, all banks idle; CKE ≥ V_IHMIN; t_CK = t_CKMIN, address and other control
inputs stable at ≥ V_IHMIN or ≤ V_ILMAX; V_IN = V_REF for DQ, DQS and DM.
Active Power-Down Standby Current: one bank active; power-down mode;
CKE ≤ V_ILMAX; t_CK = t_CKMIN; V_IN = V_REF for DQ, DQS and DM.
Active Standby Current: one bank active; CS ≥ V_IHMIN; CKE ≥ V_IHMIN; t_RC = t_RASMAX; t_CK = t_CKMIN; DQ, DM and DQS
inputs changing twice per clock cycle; address and control inputs changing once per clock cycle.
I_DD2Q
I_DD3P
I_DD3N
Operating Current: one bank active; Burst = 2; reads; continuous burst; address and control inputs changing once
per clock cycle; 50 % of data outputs changing on every clock edge; CL = 2 for DDR200 and DDR266A, CL = 3
for DDR333; t_CK = t_CKMIN; I_OUT = 0 mA
Operating Current: one bank active; Burst = 2; writes; continuous burst; address and control inputs changing once
per clock cycle; 50 % of data outputs changing on every clock edge; CL = 2 for DDR200 and DDR266A, CL = 3
for DDR333; t_CK = t_CKMIN
Auto-Refresh Current: t_RC = t_RFCMIN, burst refresh
Self-Refresh Current: CKE ≤ 0.2 V; external clock on; t_CK = t_CKMIN
Operating Current: four bank; four bank interleaving with BL = 4; Refer to the following page for detailed test
conditions.
I_DD4R
I_DD4W
I_DD5
I_DD6
I_DD7
Rev. 1.6, 2007-02
24
03292006-U5AN-6TI1