HYB25D128160C Datasheet, PDF (25/35 Pages) Qimonda AG – 128-Mbit Double-Data-Rate SDRAM

Internet Data Sheet
HYB25D128xxxC[C/E/F/T](L)
128-Mbit Double-Data-Rate SDRAM
TABLE 21
I_DD Specification
–5
–6
–7
Unit Note¹⁾/ Test Condition
DDR400B
DDR333
DDR266A
Symbol
Typ. Max.
Typ. Max.
Typ. Max.
I_DD0
70
90
60
75
50
65
mA
×4/×8 ²⁾³⁾
75
90
65
75
55
65
mA
×16
I_DD1
80
100
70
85
65
75
mA
×4/×8
95
110
80
95
70
85
mA
×16
I_DD2P
I_DD2F
I_DD2Q
I_DD3P
I_DD3N
4
5
3.5
4.5
3
4
mA
—
30
36
25
30
20
24
mA
—
20
28
17
24
15
21
mA
—
13
18
11
15
9
13
mA
—
38
45
32
38
28
36
mA
×4/×8
43
54
36
45
30
40
mA
×16
I_DD4R
85
100
70
100
120
85
85
60
100
70
70
mA
×4/×8
85
mA
×16
I_DD4W
90
105
75
100
130
90
90
65
110
75
75
mA
×4/×8
90
mA
×16
I_DD5
140
190
120
160
100
140
mA
—
I_DD6
1.4
2.8
1.4
2.8
1.4
2.8
mA
Standard version ⁴⁾
—
—
1.1
1.1
1.1
1.1
mA
Low power version ⁵⁾
I_DD7
210
250
180
215
140
170
mA
×4/×8
210
250
180
215
140
170
mA
×16
1) Test conditions for typical values: VDD = 2.5 V ( DDR266, DDR333), VDD = 2.6 V (DDR400), TA = 25 °C, test conditions for maximum
values: VDD = 2.7 V, TA = 10 °C
2) I_DD specifications are tested after the device is properly initialized and measured at 133 MHz for DDR266, 166 MHz for DDR333, and 200
MHz for DDR400.
3) Input slew rate = 1 V/ns.
4) Enables on-chip refresh and address counters.
5) L: Low power version (available on request)
Rev. 1.6, 2007-02
25
03292006-U5AN-6TI1