HYB25D128160C Datasheet, PDF (29/35 Pages) Qimonda AG – 128-Mbit Double-Data-Rate SDRAM

Internet Data Sheet
HYB25D128xxxC[C/E/F/T](L)
128-Mbit Double-Data-Rate SDRAM
Parameter
Data hold skew factor
Active to Autoprecharge delay
Active to Precharge command
Active to Active/Auto-refresh command period
Active to Read or Write delay
Average Periodic Refresh Interval
Symbol –7
DDR266A
Unit Note¹⁾/ Test
Condition
t_QHS
t_RAP
t_RAS
t_RC
t_RCD
t_REFI
Min.
—
—
t_RCD or t_RASmin
45
65
20
—
Max.
+0.75 ns
+0.75 ns
—
ns
120E+3 ns
—
ns
—
ns
15.6
µs
TFBGA
TSOPII
—
—
—
—
10)
Auto-refresh to Active/Auto-refresh command period
t_RFC
75
—
ns —
Precharge command period
t_RP
20
—
ns —
Read preamble
t_RPRE
0.9
1.0
t_CK —
Read postamble
t_RPST
0.40
0.60
t_CK —
Active bank A to Active bank B command
t_RRD
15
—
ns —
Write preamble
t_WPRE
0.25
—
t_CK —
Write preamble setup time
t_WPRES
0
—
ns ¹¹⁾
Write postamble
t_WPST
0.40
0.60
t_CK
12)
Write recovery time
t_WR
15
—
ns —
Internal write to read command delay
t_WTR
1
—
t_CK —
Exit self-refresh to non-read command
t_XSNR
75
—
ns —
Exit self-refresh to read command
t_XSRD
200
—
t_CK —
1) 0 °C ≤ T_A ≤ 70 °C; V_DDQ = 2.5 V ± 0.2 V, V_DD = +2.5 V ± 0.2 V (DDR333); V_DDQ = 2.6 V ± 0.1 V, V_DD = +2.6 V ± 0.1 V (DDR400)
2) Input slew rate ≥ 1 V/ns for DDR400, DDR333
3) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross: the input reference level for signals
other than CK/CK, is V_REF. CK/CK slew rate are ≥ 1.0 V/ns.
4) Inputs are not recognized as valid until V_REF stabilizes.
5) The Output timing reference level, as measured at the timing reference point indicated in AC Characteristics (note 3) is V_TT.
6) For each of the terms, if not already an integer, round to the next highest integer. t_CK is equal to the actual system clock cycle time.
7) t_HZ and t_LZ transitions occur in the same access time windows as valid data transitions. These parameters are not referred to a specific
voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ).
8) Fast slew rate ≥ 1.0 V/ns , slow slew rate ≥ 0.5 V/ns and < 1 V/ns for command/address and CK & CK slew rate > 1.0 V/ns, measured
between V_IH(ac) and V_IL(ac).
9) These parameters guarantee device timing, but they are not necessarily tested on each device.
10) A maximum of eight Autorefresh commands can be posted to any given DDR SDRAM device.
11) The specific requirement is that DQS be valid (HIGH, LOW, or some point on a valid transition) on or before this CK edge. A valid transition
is defined as monotonic and meeting the input slew rate specifications of the device. When no writes were previously in progress on the
bus, DQS will be transitioning from Hi-Z to logic LOW. If a previous write was in progress, DQS could be HIGH, LOW, or transitioning from
HIGH to LOW at this time, depending on t_DQSS.
12) The maximum limit for this parameter is not a device limit. The device operates with a greater value for this parameter, but system
performance (bus turnaround) degrades accordingly.
Rev. 1.6, 2007-02
29
03292006-U5AN-6TI1