HYB25D128160C Datasheet, PDF (26/35 Pages) Qimonda AG – 128-Mbit Double-Data-Rate SDRAM

Internet Data Sheet
HYB25D128xxxC[C/E/F/T](L)
128-Mbit Double-Data-Rate SDRAM
Parameter
Symbol –5
DDR400B
TABLE 22
AC Timing - Absolute Specifications
–6
DDR333
Unit Note¹⁾/ Test
Condition
DQ output access time from CK/CK t_AC
CK high-level width
t_CH
Clock cycle time
t_CK
CK low-level width
t_CL
Auto precharge write recovery +
t_DAL
precharge time
DQ and DM input hold time
DQ and DM input pulse width (each
input)
t_DH
t_DIPW
DQS output access time from CK/CK t_DQSCK
DQS input low (high) pulse width
(write cycle)
t_DQSL,H
DQS-DQ skew (DQS and associated t_DQSQ
DQ signals)
DQS-DQ skew (DQS and associated t_DQSQ
DQ signals)
Write command to 1^st DQS latching t_DQSS
transition
DQ and DM input setup time
t_DS
DQS falling edge hold time from CK t_DSH
(write cycle)
DQS falling edge to CK setup time t_DSS
(write cycle)
Clock Half Period
t_HP
Data-out high-impedance time from t_HZ
CK/CK
Address and control input hold time t_IH
Min.
Max. Min.
Max.
–0.5
+0.5 –0.7
+0.7
ns
2)3)4)5)
0.45
0.55 0.45
0.55 t_CK —
5
8
6
12
ns CL = 3.0
6
12
6
12
ns CL = 2.5
7.5
12
7.5
12
ns CL = 2.0
0.45
0.55
(t_WR/t_CK)+(t_RP/t_CK)
0.45
0.55
(t_WR/t_CK)+(t_RP/t_CK)
t_CK —
t_CK ⁶⁾
0.4
—
0.45
—
ns —
1.75
—
1.75
—
ns —
–0.5
+0.5 –0.6
+0.6 ns —
0.35
—
0.35
—
t_CK —
—
+0.40 —
+0.40 ns TFBGA
—
+0.40 —
+0.45 ns TSOPII
0.72
1.25
0.4
—
0.2
—
0.2
—
min. (t_CL, t_CH) —
—
+0.7
0.75
1.25
0.45
—
0.2
—
0.2
—
min. (t_CL, t_CH) —
–0.7
+0.7
t_CK —
ns —
t_CK —
t_CK —
ns —
ns ⁷⁾
0.6
—
0.75
—
ns fast slew rate
8)
0.7
—
0.8
—
ns slow slew rate
Control and Addr. input pulse width t_IPW
2.2
(each input)
Address and control input setup time t_IS
0.6
—
2.2
—
0.75
—
ns ⁹⁾
—
ns fast slew rate
0.7
—
0.8
—
ns slow slew rate
Rev. 1.6, 2007-02
26
03292006-U5AN-6TI1