HYS72T32000HR Datasheet, PDF (50/67 Pages) Qimonda AG – 240-Pin Registered DDR2 SDRAM Modules

Product Type
Internet Data Sheet
HYS72T[32/64]0xxHR–[2.5/3/3S/3.7/5]–A
Registered DDR2 SDRAM Modules
Organization
Label Code
JEDEC SPD Revision
Byte#
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
Description
t_AC SDRAM @ CL_MAX -1 [ns]
t_CK @ CL_MAX -2 (Byte 18) [ns]
t_AC SDRAM @ CL_MAX -2 [ns]
t_RP.MIN [ns]
t_RRD.MIN [ns]
t_RCD.MIN [ns]
t_RAS.MIN [ns]
Module Density per Rank
t_AS.MIN and t_CS.MIN [ns]
t_AH.MIN and t_CH.MIN [ns]
t_DS.MIN [ns]
t_DH.MIN [ns]
t_WR.MIN [ns]
t_WTR.MIN [ns]
t_RTP.MIN [ns]
Analysis Characteristics
t_RC and t_RFC Extension
t_RC.MIN [ns]
t_RFC.MIN [ns]
t_CK.MAX [ns]
t_DQSQ.MAX [ns]
t_QHS.MAX [ns]
PLL Relock Time
T_CASE.MAX Delta / ∆T_4R4W Delta
Psi(T-A) DRAM
∆T₀ (DT0)
∆T_2N (DT2N, UDIMM) or ∆T_2Q (DT2Q, RDIMM)
256MB
512MB
512MB
×72
×72
×72
1 Rank (×8)
1 Rank (×4)
2 Ranks (×8)
PC2–5300R–555 PC2–5300R–555 PC2–5300R–555
Rev. 1.2
Rev. 1.2
Rev. 1.2
HEX
50
50
60
3C
1E
3C
2D
40
20
27
10
17
3C
1E
1E
00
00
3C
4B
80
18
22
0F
52
82
43
25
HEX
50
50
60
3C
1E
3C
2D
80
20
27
10
17
3C
1E
1E
00
00
3C
4B
80
18
22
0F
52
82
43
25
HEX
50
50
60
3C
1E
3C
2D
40
20
27
10
17
3C
1E
1E
00
00
3C
4B
80
18
22
0F
52
82
43
25
Rev. 1.21, 2007-03
50
09152006-J5FK-C565