HYS72T32000HR Datasheet, PDF (34/67 Pages) Qimonda AG – 240-Pin Registered DDR2 SDRAM Modules

Internet Data Sheet
HYS72T[32/64]0xxHR–[2.5/3/3S/3.7/5]–A
Registered DDR2 SDRAM Modules
Parameter
Symbol Note¹⁾²⁾
3)4)5)6)
Self-Refresh Current
I_DD6
CKE ≤ 0.2 V; external clock off, CK and CK at 0 V; Other control and address inputs are FLOATING,
Data bus inputs are FLOATING. RESET is LOW. I_DD6 current values are guaranteed up to T_CASE of
85 °C max.
All Bank Interleave Read Current
I_DD7
All banks are being interleaved at minimum t_RC without violating t_RRD using a burst length of 4. Control
and address bus inputs are STABLE during DESELECTS. I_OUT = 0 mA.
1) V_DDQ = 1.8 V ± 0.1 V; V_DD = 1.8 V ± 0.1 V
2) Definitions for I_DD see Table 23
3) For two rank modules: for all active current measurements the other rank is in Precharge Power-Down Mode I_DD2P
4) RESET signal is HIGH for all currents, except for I_DD6 (Self Refresh)
5) All current measurements includes Register and PLL current consumption
6) For details and notes see the relevant QIMONDA component data sheet
Parameter
LOW
STABLE
FLOATING
SWITCHING
Description
TABLE 23
Definitions for I_DD
V_IN ≤ V_IL(ac).MAX, HIGH is defined as V_IN ≥ V_IH(ac).MIN
inputs are stable at a HIGH or LOW level
inputs are V_REF = V_DDQ /2
inputs are changing between HIGH and LOW every other clock (once per 2 cycles) for address and control
signals, and inputs changing between HIGH and LOW every other data transfer (once per cycle) for DQ
signals not including mask or strobes.
Rev. 1.21, 2007-03
34
09152006-J5FK-C565