HYS72T32000HR Datasheet, PDF (42/67 Pages) Qimonda AG – 240-Pin Registered DDR2 SDRAM Modules

Product Type
Internet Data Sheet
HYS72T[32/64]0xxHR–[2.5/3/3S/3.7/5]–A
Registered DDR2 SDRAM Modules
Organization
Label Code
JEDEC SPD Revision
Byte#
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
Description
Analysis Characteristics
t_RC and t_RFC Extension
t_RC.MIN [ns]
t_RFC.MIN [ns]
t_CK.MAX [ns]
t_DQSQ.MAX [ns]
t_QHS.MAX [ns]
PLL Relock Time
T_CASE.MAX Delta / ∆T_4R4W Delta
Psi(T-A) DRAM
∆T₀ (DT0)
∆T_2N (DT2N, UDIMM) or ∆T_2Q (DT2Q, RDIMM)
∆T_2P (DT2P)
∆T_3N (DT3N)
∆T_3P.fast (DT3P fast)
∆T_3P.slow (DT3P slow)
∆T_4R (DT4R) / ∆T_4R4W Sign (DT4R4W)
∆T_5B (DT5B)
∆T₇ (DT7)
Psi(ca) PLL
Psi(ca) REG
∆T_PLL (DTPLL)
∆T_REG (DTREG) / Toggle Rate
SPD Revision
Checksum of Bytes 0-62
Manufacturer’s JEDEC ID Code (1)
Manufacturer’s JEDEC ID Code (2)
256MB
512MB
512MB
×72
×72
×72
1 Rank (×8)
1 Rank (×4)
2 Ranks (×8)
PC2–6400R–666 PC2–6400R–666 PC2–6400R–666
Rev. 1.2
Rev. 1.2
Rev. 1.2
HEX
00
00
3C
4B
80
14
1E
0F
53
82
5B
2B
29
29
36
19
4E
17
26
C4
8C
70
B0
12
F7
7F
7F
HEX
00
00
3C
4B
80
14
1E
0F
53
82
5B
2B
29
29
36
19
4E
17
26
C4
8C
70
B0
12
31
7F
7F
HEX
00
00
3C
4B
80
14
1E
0F
53
82
5B
2B
29
29
36
19
4E
17
26
C4
8C
70
B0
12
F9
7F
7F
Rev. 1.21, 2007-03
42
09152006-J5FK-C565