HYS72T32000HR Datasheet, PDF (22/67 Pages) Qimonda AG – 240-Pin Registered DDR2 SDRAM Modules

Internet Data Sheet
HYS72T[32/64]0xxHR–[2.5/3/3S/3.7/5]–A
Registered DDR2 SDRAM Modules
27) When the device is operated with input clock jitter, this parameter needs to be derated by the actual t_JIT.DUTY of the input clock. (output
deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR2–667 SDRAM has t_JIT.DUTY.MIN = – 72 ps
and t_JIT.DUTY.MAX = + 93 ps, then t_{RPST.MIN(DERATED)} = t_RPST.MIN + t_JIT.DUTY.MIN = 0.4 x t_CK.AVG – 72 ps = + 928 ps and t_{RPST.MAX(DERATED)} = t_RPST.MAX
+ t_JIT.DUTY.MAX = 0.6 x t_CK.AVG + 93 ps = + 1592 ps. (Caution on the MIN/MAX usage!).
28) For these parameters, the DDR2 SDRAM device is characterized and verified to support t_nPARAM = RU{t_PARAM / t_CK.AVG}, which is in clock
cycles, assuming all input clock jitter specifications are satisfied. For example, the device will support t_nRP = RU{t_RP / t_CK.AVG}, which is in
clock cycles, if all input clock jitter specifications are met. This means: For DDR2–667 5–5–5, of which t_RP = 15 ns, the device will support
t_nRP = RU{t_RP / t_CK.AVG} = 5, i.e. as long as the input clock jitter specifications are met, Precharge command at Tm and Active command at
Tm + 5 is valid even if (Tm + 5 - Tm) is less than 15 ns due to input clock jitter.
29) DAL = WR + RU{t_RP(ns) / t_CK(ns)}, where RU stands for round up. WR refers to the tWR parameter stored in the MRS. For t_RP, if the result
of the division is not already an integer, round up to the next highest integer. t_CK refers to the application clock period. Example: For
DDR2–533 at t_CK = 3.75 ns with t_WR programmed to 4 clocks. t_DAL = 4 + (15 ns / 3.75 ns) clocks = 4 + (4) clocks = 8 clocks.
30) t_DAL.nCK = WR [nCK] + t_nRP.nCK = WR + RU{t_RP [ps] / t_CK.AVG[ps] }, where WR is the value programmed in the EMR.
31) t_WTR is at lease two clocks (2 x t_CK) independent of operation frequency.
32) t_CKE.MIN of 3 clocks means CKE must be registered on three consecutive positive clock edges. CKE must remain at the valid input level the
entire time it takes to achieve the 3 clocks of registration. Thus, after any CKE transition, CKE may not transition from its valid level during
the time period of t_IS + 2 x t_CK + t_IH.
33) ODT turn on time min is when the device leaves high impedance and ODT resistance begins to turn on. ODT turn on time max is when
the ODT resistance is fully on. Both are measured from t_AOND.
34) ODT turn off time min is when the device starts to turn off ODT resistance. ODT turn off time max is when the bus is in high impedance.
Both are measured from t_AOFD.
35) When the device is operated with input clock jitter, this parameter needs to be derated by {–t_JIT.DUTY.MAX – t_{ERR(6-10PER).MAX}} and {–t_JIT.DUTY.MIN
– t_{ERR(6-10PER).MIN} } of the actual input clock. (output deratings are relative to the SDRAM input clock.) For example, if the measured jitter
into a DDR2–667 SDRAM has t_{ERR(6-10PER).MIN} = – 272 ps, t_{ERR(6- 10PER).MAX} = + 293 ps, t_JIT.DUTY.MIN = – 106 ps and t_JIT.DUTY.MAX = + 94 ps,
then t_{AOF.MIN(DERATED)} = t_AOF.MIN + {– t_JIT.DUTY.MAX – t_{ERR(6-10PER).MAX}} = – 450 ps + {– 94 ps – 293 ps} = – 837 ps and t_{AOF.MAX(DERATED)} = t_AOF.MAX
+ {– t_JIT.DUTY.MIN – t_{ERR(6-10PER).MIN}} = 1050 ps + {106 ps + 272 ps} = + 1428 ps. (Caution on the MIN/MAX usage!)
Parameter
Symbol
DQ output access time from CK / CK
t_AC
DQS output access time from CK / CK
t_DQSCK
Average clock high pulse width
t_CH.AVG
Average clock low pulse width
t_CL.AVG
Average clock period
t_CK.AVG
DQ and DM input setup time
t_DS.BASE
DQ and DM input hold time
t_DH.BASE
Control & address input pulse width for each input t_IPW
DQ and DM input pulse width for each input
t_DIPW
Data-out high-impedance time from CK / CK
t_HZ
DQS/DQS low-impedance time from CK / CK
t_LZ.DQS
DQ low impedance time from CK/CK
t_LZ.DQ
DQS-DQ skew for DQS & associated DQ signals t_DQSQ
CK half pulse width
t_HP
DQ hold skew factor
t_QHS
DQ/DQS output hold time from DQS
t_QH
Write command to DQS associated clock edges WL
TABLE 17
Timing Parameter by Speed Grade - DDR2–667
DDR2–667
Min.
Max.
Unit
Note^{1)2)3)4)5)6)7)}
8)
–450
–400
0.48
0.48
3000
100
175
+450
+400
0.52
0.52
8000
—
—
ps
ps
t_CK.AVG
t_CK.AVG
ps
ps
ps
9)
9)
10)11)
10)11)
—
12)13)14)
13)14)15)
0.6
0.35
—
t_AC.MIN
2 x t_AC.MIN
—
Min (t_CH.ABS,
t_CL.ABS)
—
t_HP – t_QHS
RL–1
—
—
t_AC.MAX
t_AC.MAX
t_AC.MAX
240
__
340
—
t_CK.AVG
t_CK.AVG
ps
ps
ps
ps
ps
—
—
9)16)
9)16)
9)16)
17)
18)
ps
19)
ps
20)
nCK —
Rev. 1.21, 2007-03
22
09152006-J5FK-C565