HYS72T32000HR Datasheet, PDF (23/67 Pages) Qimonda AG – 240-Pin Registered DDR2 SDRAM Modules

Internet Data Sheet
HYS72T[32/64]0xxHR–[2.5/3/3S/3.7/5]–A
Registered DDR2 SDRAM Modules
Parameter
Symbol
DQS latching rising transition to associated clock t_DQSS
edges
DQS input high pulse width
DQS input low pulse width
DQS falling edge to CK setup time
DQS falling edge hold time from CK
Write postamble
Write preamble
Address and control input setup time
Address and control input hold time
Read preamble
Read postamble
Active to precharge command
Active to active command period for 1KB page
size products
t_DQSH
t_DQSL
t_DSS
t_DSH
t_WPST
t_WPRE
t_LS.BASE
t_LH.BASE
t_RPRE
t_RPST
t_RAS
t_RRD
Active to active command period for 2KB page t_RRD
size products
Four Activate Window for 1KB page size products t_FAW
Four Activate Window for 2KB page size products t_FAW
CAS to CAS command delay
t_CCD
Write recovery time
t_WR
Auto-Precharge write recovery + precharge time t_DAL
Internal write to read command delay
t_WTR
Internal Read to Precharge command delay
t_RTP
Exit self-refresh to a non-read command
t_XSNR
Exit self-refresh to read command
t_XSRD
Exit precharge power-down to any valid
t_XP
command (other than NOP or Deselect)
Exit power down to read command
Exit active power-down mode to read command
(slow exit, lower power)
t_XARD
t_XARDS
CKE minimum pulse width ( high and low pulse t_CKE
width)
ODT turn-on delay
ODT turn-on
ODT turn-on (Power down mode)
t_AOND
t_AON
t_AONPD
ODT turn-off delay
ODT turn-off
ODT turn-off (Power down mode)
t_AOFD
t_AOF
t_AOFPD
DDR2–667
Min.
– 0.25
Max.
+ 0.25
0.35
—
0.35
—
0.2
—
0.2
—
0.4
0.6
0.35
—
200
—
275
—
0.9
1.1
0.4
0.6
45
70000
7.5
—
Unit
Note^{1)2)3)4)5)6)7)}
8)
t ²¹⁾
CK.AVG
t_CK.AVG
t_CK.AVG
t_CK.AVG
t_CK.AVG
t_CK.AVG
t_CK.AVG
ps
ps
t_CK.AVG
t_CK.AVG
ns
ns
—
—
21)
21)
—
—
22)23)
23)24)
25)26)
25)27)
28)
28)
10
—
37.5
—
50
—
2
—
15
—
WR + t_nRP
—
7.5
—
7.5
—
t_RFC +10
—
200
—
2
—
ns
28)
ns
ns
nCK
ns
nCK
ns
ns
ns
nCK
nCK
28)
28)
—
28)
29)30)
28)31)
28)
28)
—
—
2
—
7 – AL
—
nCK —
nCK —
3
—
nCK ³²⁾
2
t_AC.MIN
t_AC.MIN + 2
2.5
t_AC.MIN
t_AC.MIN + 2
2
t_AC.MAX + 0.7
2 x t_CK.AVG +
t_AC.MAX + 1
2.5
t_AC.MAX + 0.6
2.5 x t_CK.AVG +
t_AC.MAX + 1
nCK
ns
ns
nCK
ns
ns
—
9)33)
—
—
34)35)
—
Rev. 1.21, 2007-03
23
09152006-J5FK-C565