HYB25D512800BT Datasheet, PDF (32/38 Pages) Infineon Technologies AG – 512Mbit Double Data Rate SDRAM

Internet Data Sheet
HYB25D512[40/16/80]0B[E/F/C/T](L)
Double-Data-Rate SDRAM
TABLE 22
I_DD Specification
–7
–6
–5
Unit Note¹⁾/Test Condition
DDR266A
DDR333
DDR400B
Symbol
Typ. Max. Typ. Max. Typ. Max.
I_DD0
65
78
75
90
80
100
mA
×4/×8 ²⁾³⁾
80
95
90
110
100
120
mA
×16 ³⁾
I_DD1
75
90
85
100
90
110
mA
×4/×8 ³⁾
90
110
105
125
115
140
mA
×16 ³⁾
I_DD2P
I_DD2F
I_DD2Q
I_DD3P
I_DD3N
1.5
4
20
24
15
21
9
13
29
35
31
37
1.6
4
25
30
17
24
11
15
35
41
37
44
1.7
4
30
36
19
26
12
16
39
47
42
50
mA
3)
mA
3)
mA
3)
mA
3)
mA
×4/×8 ³⁾
mA
×16 ³⁾
I_DD4R
67
78
77
90
85
100
mA
×4/×8 ³⁾
85
100
105
125
120
145
mA
×16 ³⁾
I_DD4W
71
83
81
95
90
105
mA
×4/×8 ³⁾
90
105
110
130
125
150
mA
×16 ³⁾
I_DD5
170
205
185
220
205
245
mA
3)4)
I_DD6
2.6
5.0
2.7
5.0
2.8
5.0
mA
3)
2.5
2.5
2.5
2.5
2.5
2.5
mA
low power
I_DD7
204
243
234
279
260
310
mA
×4/×8 ³⁾
215 255
255
310
285
340
mA
×16 ³⁾
1) Test conditions for typical values: V_DD = 2.5 V (DDR266, DDR333), V_DD = 2.6 V (DDR400), T_A = 25 °C, test conditions for maximum values:
V_DD = 2.7 V, T_A = 10 °C
2) I_DD specifications are tested after the device is properly initialized and measured at 133 MHz for DDR266, 166 MHz for DDR333, and 200
MHz for DDR400.
3) Input slew rate = 1 V/ns.
4) Enables on-chip refresh and address counters.
Rev. 1.63, 2006-09
32
03062006-PFFJ-YJY2