HYB25D512800BT Datasheet, PDF (14/38 Pages) Infineon Technologies AG – 512Mbit Double Data Rate SDRAM

Internet Data Sheet
HYB25D512[40/16/80]0B[E/F/C/T](L)
Double-Data-Rate SDRAM
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Z
Z
Z
Z
Field Bits
BL [2:0]
BT 3
CL [6:4]
MODE [12:7]
Type
w
w
w
w
TABLE 7
Mode Register Definition
Description
Burst Length
Number of sequential bits per DQ related to one read/write command.
Note: All other bit combinations are RESERVED.
001_B 2
010_B 4
011_B 8
Burst Type
See Table 8 for internal address sequence of low order address bits.
0_B Sequential
1_B Interleaved
CAS Latency
Number of full clocks from read command to first data valid window.
Note: All other bit combinations are RESERVED.
010_B 2
011_B 3
101_B (1.5 Optional, not covered by this data sheet)
110_B 2.5
Operating Mode
Note: All other bit combinations are RESERVED.
000000_B Normal Operation without DLL Reset
000010_B DLL Reset
Rev. 1.63, 2006-09
14
03062006-PFFJ-YJY2