HYB25D512800BT Datasheet, PDF (29/38 Pages) Infineon Technologies AG – 512Mbit Double Data Rate SDRAM

Internet Data Sheet
HYB25D512[40/16/80]0B[E/F/C/T](L)
Double-Data-Rate SDRAM
7) t_HZ and t_LZ transitions occur in the same access time windows as valid data transitions. These parameters are not referred to a specific
voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ).
8) Fast slew rate ≥ 1.0 V/ns , slow slew rate ≥ 0.5 V/ns and < 1 V/ns for command/address and CK & CK slew rate > 1.0 V/ns, measured
between V_IH(ac) and V_IL(ac).
9) These parameters guarantee device timing, but they are not necessarily tested on each device.
10) The specific requirement is that DQS be valid (HIGH,LOW, or some point on a valid transition) on or before this CK edge. A valid transition
is defined as monotonic and meeting the input slew rate specificationsof the device. When no writes were previously in progress on the
bus, DQS will be transitioning from Hi-Z to logic LOW. If a previous write was in progress, DQS could be HIGH, LOW at this time, depending
on t_DQSS.
11) The maximum limit for this parameter is not a device limit. The device operates with a greater value for this parameter, but system
performance (bus turnaround) degrades accordingly.
Parameter
Symbol
DQ output access time from CK/CK
t_AC
CK high-level width
t_CH
Clock cycle time
t_CK
CK low-level width
Auto precharge write recovery + precharge time
DQ and DM input hold time
DQ and DM input pulse width (each input)
DQS output access time from CK/CK
DQS input low (high) pulse width (write cycle)
DQS-DQ skew (DQS and associated DQ signals)
Write command to 1^st DQS latching transition
DQ and DM input setup time
DQS falling edge hold time from CK (write cycle)
DQS falling edge to CK setup time (write cycle)
Clock Half Period
Data-out high-impedance time from CK/CK
Address and control input hold time
t_CL
t_DAL
t_DH
t_DIPW
t_DQSCK
t_DQSL,H
t_DQSQ
t_DQSS
t_DS
t_DSH
t_DSS
t_HP
t_HZ
t_IH
Control and Addr. input pulse width (each input) t_IPW
Address and control input setup time
t_IS
Data-out low-impedance time from CK/CK
t_LZ
TABLE 20
AC Timing - Absolute Specifications for PC2100
–7
DDR266A
Unit
Note¹⁾/Test
Condition
Min.
Max.
–0.75
+0.75 ns
0.45
7.5
0.55
t_CK
12
ns
7.5
12
ns
7.5
12
ns
0.45
0.55
t_CK
(t_WR/t_CK)+(t_RP/t_CK) —
t_CK
0.5
—
ns
1.75
—
ns
–0.75
+0.75 ns
0.35
—
—
t_CK
+0.5
ns
0.75
0.5
1.25
t_CK
—
ns
0.2
0.2
min. (t_CL, t_CH)
–0.75
—
t_CK
—
t_CK
ns
+0.75 ns
0.9
—
ns
1.0
—
ns
2.2
—
ns
0.9
—
ns
1.0
—
ns
–0.75
+0.75 ns
2)3)4)5)
2)3)4)5)
CL = 3.0^2)3)4)5)
CL = 2.5^2)3)4)5)
CL = 2.0^2)3)4)5)
2)3)4)5)
2)3)4)5)6)
2)3)4)5)
2)3)4)5)6)
2)3)4)5)
2)3)4)5)
TSOPII ^2)3)4)5)
2)3)4)5)
2)3)4)5)
2)3)4)5)
2)3)4)5)
2)3)4)5)
2)3)4)5)7)
fast slew rate
3)4)5)6)8)
slow slew rate
3)4)5)6)8)
2)3)4)5)9)
fast slew rate
3)4)5)6)8)
slow slew rate
3)4)5)6)8)
2)3)4)5)7)
Rev. 1.63, 2006-09
29
03062006-PFFJ-YJY2