PM73122 Datasheet, PDF (344/489 Pages) PMC-Sierra, Inc – 32 LINK CES/DBCES AAL1 SAR PROCESSOR

RELEASED
DATASHEET
PMC-1981419
ISSUE 7
PM73122 AAL1GATOR-32
32 LINK CES/DBCES AAL1 SAR PROCESSOR
Register 0x80501H: Insert FIFO Underrun Interrupt Status Register
(INS_FI_URI)
Bit
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Type
Rsvd
Rsvd
Rsvd
Rsvd
Rsvd
Rsvd
Rsvd
Rsvd
RO
RO
RO
RO
RO
RO
RO
R2C
Function
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
LINK_GRP_HIGH
LINK_GRP_LOW
LINK[4]
LINK[3]
LINK[2]
LINK[1]
LINK[0]
FIFO_UDRI
Default
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
Back to back reads of this register must be at least 250 ns apart.
FIFO_UDRI
This bit is set when a FIFO underrun is detected. Only one error can be
reported at a time. However errors are latched internally so that if multiple
errors occur, any pending errors will be reported when the first one is cleared.
If this bit is set and DC_EN is not set for that tributary and SYNCH_TRIB is
not set for any tributary, then the tributary mapped to the link specified by
LINK below should be reset by writing to the EXT_TRIB_CTL register. If
DC_EN is set and SYNCH_TRIB is not set for any tributaries, then the
tributary will be automatically reset.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
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