PM73122 Datasheet, PDF (290/489 Pages) PMC-Sierra, Inc – 32 LINK CES/DBCES AAL1 SAR PROCESSOR

RELEASED
DATASHEET
PMC-1981419
ISSUE 7
PM73122 AAL1GATOR-32
32 LINK CES/DBCES AAL1 SAR PROCESSOR
Register 0x80122: UI Sink Config Reg (UI_SNK_CFG)
Bit
Type
Function
Default
15:6
R
Unused
X
5
R/W
CS_MODE_EN
0
4
R/W
16_BIT_MODE
0
3
R/W
EVEN_PAR
0
2
R/W
ANY-PHY_EN
0
1:0
R/W
UTOP_MODE
00
This register controls the sink side configuration of the Utopia Interface
UTOP_MODE(1:0)
Selects the operating mode for the sink side interface:
00 Utopia-1 Master
01 Utopia-1 Slave
10 Utopia-2 Single Address Slave
11 Utopia-2 Multi-Address Slave
ANY-PHY_EN
Enables Any-PHY mode for sink side interface.
0) UTOPIA mode. (Use UTOP_MODE for UTOPIA type)
1) Any-PHY mode.
EVEN_PAR
Determines the checked parity across data bytes/words received by the sink
interface.
0) Odd parity
1) Even parity.
16_BIT_MODE
When set, UI sink side interface operates in 16-bit mode.
0) 8-bit mode
1) 16-bit mode
CS_MODE_EN
When set, TPHY_ADDR(3)/TCSB input pin is used as a chip select (TCSB)
for the sink side interface, when clear TPHY_ADDR(3)/TCSB is used as a
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
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