PM73122 Datasheet, PDF (259/489 Pages) PMC-Sierra, Inc – 32 LINK CES/DBCES AAL1 SAR PROCESSOR

RELEASED
DATASHEET
PMC-1981419
ISSUE 7
PM73122 AAL1GATOR-32
32 LINK CES/DBCES AAL1 SAR PROCESSOR
Field (Bits)
R_BYTES_CELL
(14:9)
R_AAL0_MODE
(8)
R_CDVT
(7:0)
Description
A 6-bit integer specifying how many bytes per cell
are required if no structure pointers are used. For
UDF-HS mode, this must be set to 47. In other
modes, set this to the partially filled length. If cells
are not partially filled, set this to 47.
If set, treats this queue as an AAL0 queue and will
write all 48 bytes of payload into the allocated time
slots. Use R_BYTES_CELL=x30 for full AAL0 cells.
Receive Cell Delay Variation Tolerance (R_CDVT)
is a constant and is programmed by the
microprocessor during initialization. It is used by the
RFTC after the receipt of the first cell after an
underrun. In T1 SDF-FR, T1 SDF-MF, and
E1_WITH_T1_SIG, modes, R_CDVT is expressed
as the number of multiframes in bits 7:5 and the
number of frames in bits 4:0. In E1 and all other T1
modes, R_CDVT is the number of frames. In
unstructured applications, the number of frames
refers to the number of 256-bit increments. For T1
unstructured modes, this is equivalent to the
number of 165.8 us periods. For Robust SN
Processing, this field represents the R_CDVT
desired plus the number of frames stored in the cell
that is conditionally stored. The minimum
recommended value is R_CDVT=2.
R_STATE_1 Word Format (02_H)
This word is read-only and is maintained by the RALP. This register is located
inside the chip and is reset to “0000”
Field (Bits)
Description
Reserved (FRC_UNDRN) Initialize to 0 to maintain future software
(15)
compatibility.
Reserved (SNCRCST) Initialize to 0 to maintain future software
(14)
compatibility.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
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