TDA8020HL Datasheet, PDF (9/24 Pages) NXP Semiconductors – Dual smart card interface

Philips Semiconductors
Dual smart card interface
Product specification
TDA8020HL
READING STATUS
START, ADDRESS, READ, STATUS byte, STOP.
Table 4 STATUS bits (all bits cleared after power-on, except SUPL and PRES)
NAME
PRES
PRESL
I/O
SUPL
PROT
MUTE
EARLY
ACTIVE
BIT
DESCRIPTION
0 set when the card is present; reset when the card is not present
1 set when the card has been inserted or extracted; reset when the status has been read
2 set when I/O is HIGH and reset if I/O is LOW
3 set when the supervisor has signalled a fault; reset when the status has been read
4 set when an overload or an overheating has occurred during a session; reset when the
status has been read
5 set during ATR when the selected card has not answered during the ISO 7816 time slots
6 set during ATR when the selected card has answered too early
7 set if the card is active; reset if the card is inactive
When one of the bits PRESL, MUTE, EARLY and PROT is set, then pin IRQ goes LOW until the status byte has been
read. After power-on, bit SUPL is set until the status byte has been read, and pin IRQ is LOW until the supervisor
becomes inactive.
DC/DC converter
V_CC1 is the supply voltage for card 1 contacts, V_CC2 for
card 2 contacts. Card 1 and card 2 may be independently
powered-down, powered at 5 V or powered at 3 V. A
capacitor type step-up converter is used for generating
these voltages. This step-up converter acts either as a
doubler, tripler or follower.
If V_CC is the maximum value of V_CC1 and V_CC2, then there
are 4 possible situations:
• V_DD = 3 V and V_CC = 3 V: in this case, the DC/DC
converter acts as a doubler with a regulation of
approximately 4.0 V
• V_DD = 3 V and V_CC = 5 V: in this case, the DC/DC
converter acts as a tripler with a regulation of
approximately 5.5 V
• V_DD = 5 V and V_CC = 3 V: in this case, the DC/DC
converter acts as a follower: V_DD is applied on V_UP
• V_DD = 5 V and V_CC = 5 V: in this case, the DC/DC
converter acts as a doubler with a regulation of
approximately 5.5 V.
The switch between the modes is automatically executed
when V_DD is approximately 3.4 V.
Each card may independently draw a current up to 65 mA,
also during activation, with a supply voltage from 2.5 V up
to 6.5 V provided the sum of I_CC1 and I_CC2 does not
exceed 80 mA.
If V_DD > 3 V, for 5 V cards, then both cards can draw up to
55 mA at the same time.
If V_DD > 3.3 V, for 3 V cards, then both cards can draw up
to 50 mA at the same time.
The DC/DC converter is powered with specific pins (V_DDA
and AGND) to enable separate decoupling.
The output voltage, V_UP, is internally fed to the V_CC
generators. V_CC1, V_CC2 and CGND1, CGND2 are used as
a reference for all other cards contacts.
Sequencers and clock counter
Two sequencers are used to ensure activation and
deactivation sequences according to ISO 7816 and
EMV norms, even in the event of an emergency (card
removal during transaction, supply drop-out and hardware
problem).
The sequencers are clocked by the internal oscillator.
The activation of a card is initiated by setting the card
select bit and the start bit within the control register. This is
only possible if the card is present and if the voltage
supervisor is not active.
During activation the DC/DC converter is initiated (except
if another card is already powered up or if V_DD = 5 V and
V_CC = 3 V). V_CC then goes high to the selected voltage
(3 or 5 V), the I/O lines are then enabled and the clock is
started with RST LOW.
2001 Aug 15
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