TDA8020HL Datasheet, PDF (15/24 Pages) NXP Semiconductors – Dual smart card interface

Philips Semiconductors
Dual smart card interface
Product specification
TDA8020HL
SYMBOL
PARAMETER
CONDITIONS
Clock output to the cards (pins CLK1 and CLK2)
V_o(inactive) output voltage in inactive
mode
I_inactive
V_OL
V_OH
t_r
t_f
f_clk
current from pin CLK when
inactive
LOW-level output voltage
HIGH-level output voltage
rise time
fall time
clock frequency
δ
duty factor
SR
slew rate (rise and fall)
Data lines (pins I/O1 and I/O2); note 2
no load
I_inactive = 1 mA
pin grounded
I_OL = 200 µA
I_OH < −200 µA
C_L = 30 pF
C_L = 30 pF
1 MHz Idle configuration
operational
C_L = 30 pF
C_L = 30 pF
V_o(inactive)
I_inactive
V_OL
V_OH
I_edge
t_d(edge)
V_IL
V_IH
I_IL
I_LIH
t_i(r), t_i(f)
t_o(r), t_o(f)
C_i
R_pu(int)
output voltage in inactive
mode
current from pin I/O when
inactive
no load
I_inactive = 1 mA
pin grounded
LOW-level output voltage
HIGH-level output voltage
I_OL = 1 mA
no DC load
current from pins I/O1
and I/O2 when active pull-up
I_OH < −20 µA
I_OH < −40 µA
V_OH = 0.9V_CC; C_L = 80 pF
delay between falling edge
on pins I/O1, I/O2, I/O1uC,
I/O2uC and width of active
pull-up pulse
LOW-level input voltage
HIGH-level input voltage
LOW-level input current on V_IL = 0
pin I/O
HIGH-level input leakage
current on pin I/O
V_IH = V_CC
input transition times
from V_IL(max) to V_IH(min)
output transition times
input capacitance on
pins I/O1 and I/O2
C_L < 80 pF; no DC load;
10% to 90% from 0 to
V_CC1 and V_CC2
internal pull-up resistance
between pin I/O and V_CC
2001 Aug 15
15
MIN. TYP. MAX. UNIT
0
−
0.1
0
−
0.3
0
−
−1
0
−
0.3
V_CC − 0.5 −
V_CC
−
−
8
−
−
8
1
−
1.5
0
−
10
45
−
55
0.2
−
−
V
V
mA
V
V
ns
ns
MHz
MHz
%
V/ns
0
−
−
−
−
−
0
−
0.9V_CC −
0.8V_CC −
0.75V_CC −
−1
−
−
500
0.1
V
0.3
V
−1
mA
0.3
V
V_CC + 0.1 V
V_CC + 0.1 V
V_CC + 0.1 V
−
mA
650
ns
−0.3
−
+0.8
V
1.5
−
V_CC
V
−
−
600
µA
−
−
10
µA
−
−
1.5
µs
−
−
0.1
µs
−
−
10
pF
12
15
18
kΩ