TDA8020HL Datasheet, PDF (17/24 Pages) NXP Semiconductors – Dual smart card interface

Philips Semiconductors
Dual smart card interface
Product specification
TDA8020HL
SYMBOL
PARAMETER
CONDITIONS
MIN. TYP. MAX. UNIT
Clock inputs (pins CLKIN1 and CLKIN2)
f_ext
external frequency applied
on CLKIN1 and CLKIN2
0
−
25
MHz
V_IL
V_IH
t_i(r), t_i(f)
LOW-level input voltage
HIGH-level input voltage
input transition times
0
−
0.7V_DDI −
−
−
0.25V_DDI V
V_DDI + 0.3 V
100
ns
Logic inputs (pins SAD0 and SAD1)
V_IL
LOW-level input voltage
V_IH
HIGH-level input voltage
I_LIL
LOW-level input leakage
current
−0.3
−
0.7V_DDI −
−
−
0.25V_DDI V
V_DDI + 0.3 V
±20
µA
I_LIH
HIGH-level input leakage
current
−
−
±20
µA
C_i
input capacitance
−
−
10
pF
Interrupt line (pin IRQ; open-drain; active LOW output)
V_OL
LOW-level output voltage I_o = 2 mA
I_LH
HIGH-level leakage current
−
−
0.3
V
−
−
10
µA
Serial data input/output (pin SDA; open-drain)
V_IL
LOW-level input voltage
−0.3
−
0.25V_DDI V
V_IH
HIGH-level input voltage
0.7V_DDI −
V_DDI + 0.3 V
I_LH
HIGH-level leakage current
−
−
1
µA
I_IL
LOW-level input current
depends on the pull-up resistance −
−
−
V_OL
LOW-level output voltage I_OL = 3 mA
−
−
0.3
V
Serial clock input (pin SCL; open-drain)
V_IL
LOW-level input voltage
−0.3
−
0.25V_DDI V
V_IH
HIGH-level input voltage
0.7V_DDI −
V_DDI + 0.3 V
I_LH
HIGH-level leakage current
−
−
1
µA
I_IL
LOW-level input current
depends on the pull-up resistance −
−
−
Notes
1. Two ceramic multilayer capacitors of minimum 100 nF with low ESR should be used in order to meet these
specifications.
2. Pin I/O1 has an internal 15 kΩ pull-up resistor to V_CC1 and pin I/O2 has an internal 15 kΩ pull-up resistor to V_CC2.
3. Pins I/O1uC and I/O2uC have an internal 22 kΩ pull-up resistor to V_DDI.
2001 Aug 15
17