TDA8020HL Datasheet, PDF (8/24 Pages) NXP Semiconductors – Dual smart card interface

Philips Semiconductors
Dual smart card interface
Product specification
TDA8020HL
WRITING COMMANDS
START, ADDRESS, WRITE, CONTROL byte, STOP.
Table 2 CONTROL bits (all bits cleared after power-on)
NAME
START/STOP
WARM
3 and 5 V
PDOWN
CLKPD
CLKSEL1
CLKSEL2
I/OEN
BIT
DESCRIPTION
0 when set, initiates an activation and a cold reset procedure; when reset, initiates a
deactivation sequence
1 when set, initiates a warm reset procedure; automatically reset by hardware when the card
starts answering or when the card is declared mute
2 when set, V_CC = 3 V; when reset, V_CC = 5 V
3 when set, the configuration defined by bit CLKPD is applied on pin CLK, and the circuit
enters the Power-down mode; when reset, the circuit goes back to normal (active) mode
4 when set, CLK is stopped HIGH during Power-down mode; when reset, CLK is stopped LOW
in Power-down mode
5 bits 5 and 6 determine the clock to the card in normal mode according to Table 3
6
7 when set, I/O is transferred on I/OuC; when reset, I/O to I/OuC is high-impedance
When deactivating the card, by resetting the START bit,
only bit 0 must be changed.
The clock to the cards in active mode is selected with
bits CLKSEL1 and CLKSEL2; see Table 3.
Table 3 Selecting the card clock.
BIT CLKSEL2
0
0
1
1
BIT CLKSEL1
0
1
0
1
CLOCK
OUTPUT
CLKIN/8
CLKIN/4
CLKIN/2
CLKIN
All frequency changes are synchronous, thus ensuring
that no pulse is shorter than 45% of the smallest period.
For cards power reduction modes, CLKIN may be stopped
after switching to STOP LOW or STOP HIGH. CLKIN
should be restarted before leaving this mode.
A correct duty factor can not be guaranteed in the CLKIN
configuration, as it depends on the duty factor of the
CLKIN signal.
2001 Aug 15
8