TDA8020HL Datasheet, PDF (5/24 Pages) NXP Semiconductors – Dual smart card interface

Philips Semiconductors
Dual smart card interface
Product specification
TDA8020HL
PINNING
SYMBOL
PRES1
CGND1
CLK1
V_CC1
RST1
I/O2
PRES2
CGND2
CLK2
V_CC2
RST2
GND
V_UP
SAP
SBP
V_DDA
SBM
AGND
SAM
V_DD
SCL
SDA
SAD0
SAD1
IRQ
CLKIN1
I/O1uC
I/O2uC
CLKIN2
C_DEL
V_DDI
I/O1
PIN
DESCRIPTION
1
card 1 presence contact input (active HIGH)
2
ground connection output to card 1 (C5 contact)
3
clock output to card 1 (C3 contact)
4
supply voltage output to card 1 (C1 contact); decouple to pin CGND1 with 2 × 100 nF
capacitors with ESR < 100 mΩ
5
reset output to card 1 (C2 contact)
6
I/O contact to card 2 (C7 contact); internal 15 kΩ pull-up resistance to pin V_CC2
7
card 2 presence contact input (active HIGH)
8
ground connection output to card 2 (C5 contact)
9
clock output to card 2 (C3 contact)
10 supply voltage output to card 2 (C1 contact); decouple to pin CGND2 with 2 × 100 nF
capacitors with ESR < 100 mΩ
11 reset output to card 2 (C2 contact)
12 ground connection
13 output of DC/DC converter; a 220 nF capacitor with ESR < 100 mΩ must be connected
to pin AGND
14 capacitors connection for the DC/DC converter; a 220 nF capacitor with
ESR < 100 mΩ must be connected between pins SAP and SAM
15 capacitors connection for the DC/DC converter; a 220 nF capacitor with
ESR < 100 mΩ must be connected between pins SBP and SBM
16 analog supply voltage for the DC/DC converter
17 capacitors connection for the DC/DC converter; a 220 nF capacitor with
ESR < 100 mΩ must be connected between pins SBP and SBM
18 analog ground connection for the DC/DC converter
19 capacitors connection for the DC/DC converter; a 220 nF capacitor with
ESR < 100 mΩ must be connected between pins SAP and SAM
20 power supply voltage
21 serial clock input of the I²C-bus (open drain)
22 serial data input/output of the I²C-bus (open drain)
23 I²C-bus address selection input 0
24 I²C-bus address selection input 1
25 interrupt request output to host (open drain; active LOW)
26 external clock input for card 1
27 I/O connection to host for card 1; internal 22 kΩ pull-up resistor to V_DDI
28 I/O connection to host for card 2; internal 22 kΩ pull-up resistor to V_DDI
29 external clock input for card 2
30 delay capacitor connection for the voltage supervisor (1 ms per 2 nF)
31 interface signals reference supply voltage
32 I/O contact to card 1 (C7 contact); internal 15 kΩ pull-up resistor to V_CC1
2001 Aug 15
5