SAA5X9X Datasheet, PDF (9/68 Pages) NXP Semiconductors – Economy teletext and TV microcontrollers

Philips Semiconductors
Economy teletext and TV microcontrollers
Preliminary specification
SAA5x9x family
SYMBOL
LRGBREF
B
G
R
VDS
HSYNC
VSYNC
V_DDA
V_DDT
OSCGND
XTALIN
XTALOUT
RESET
V_DDM
P1.0/INT1
P1.1/T0
P1.2/INT0
P1.3/INT1
P1.6/SCL
P1.7/SDA
P1.4
P1.5
REF+
REF−
RD
WR
PSEN
ALE
EA
AD0 to AD7
A8 to A15
PIN
SDIP52 QFP80
DESCRIPTION
31
39 DC input voltage to define the output HIGH level on the RGB pins.
32
40 Pixel rate output of the BLUE colour information.
33
41 Pixel rate output of the GREEN colour information.
34
42 Pixel rate output of the RED colour information.
35
43 Video/data switch push-pull output for dot rate fast blanking.
36
45 Schmitt trigger input for a TTL level version of the horizontal sync pulse; the
polarity of this pulse is programmable by register bit TXT1.H POLARITY.
37
47 Schmitt trigger input for a TTL level version of the vertical sync pulse;
the polarity of this pulse is programmable by register bit TXT1.V POLARITY.
38
49 +5 V analog power supply.
39
51 +5 V teletext power supply.
40
56 Crystal oscillator ground.
41
57 12 MHz crystal oscillator input.
42
58 12 MHz crystal oscillator output.
43
59 If the reset input is HIGH for at least 3 machine cycles (36 oscillator periods)
while the oscillator is running, the device is reset; this pin should be
connected to V_DDM via a 2.2 µF capacitor.
44
62 +5 V microcontroller power supply.
45
63 Port 1: 8-bit open-drain bidirectional port with alternate functions.
46
64
P1.0/INT1 is external interrupt 1 which can be triggered on the rising and
47
60 falling edge of the pulse.
48
61
P1.1/T0 is the counter/timer 0.
49
65
P1.2/INT0 is external interrupt 0.
50
66
51
67
P1.3/T1 is the counter/timer 1.
52
68
P1.6/SCL is the serial clock input for the I²C-bus.
P1.7/SDA is the serial data port for the I²C-bus.
−
50 Positive reference voltage for software driven ADC.
−
19 Negative reference voltage for software driven ADC.
−
10 Read control signal to external Data Memory.
−
11 Write control signal to external Data Memory.
−
17 Enable signal for external Program Memory.
−
18 External latch enable signal; active HIGH.
−
13 Control signal used to select external (LOW) or internal (HIGH) Program
Memory.
−
69 to 76 Address lines A0 to A7 multiplexed with data lines D0 to D7.
−
55 to 52, Address lines A8 to A15.
35 to 32
1997 Jul 07
9