SAA5X9X Datasheet, PDF (10/68 Pages) NXP Semiconductors – Economy teletext and TV microcontrollers

Philips Semiconductors
Economy teletext and TV microcontrollers
Preliminary specification
SAA5x9x family
7 FUNCTIONAL DESCRIPTION
7.1 Microcontroller
The functionality of the microcontroller used in this family
is described here with reference to the industry-standard
80C51 microcontroller. A full description of its functionality
can be found in the “80C51-Based 8-Bit Microcontrollers;
Data Handbook IC20”. Using the 80C51 as a reference,
the changes made to this family fall into two categories:
• Features not supported by the SAA529x, SAA529xA or
SAA549x devices
• Features found on the SAA529x, SAA529xA or
SAA549x devices but not supported by the 80C51.
7.2 80C51 features not supported
7.2.1 INTERRUPT PRIORITY
The IP SFR is not implemented and all interrupts are
treated with the same priority level. The normal
prioritisation of interrupts is maintained within the level.
Table 2 Interrupts and vectors address
INTERRUPT SOURCE
Reset
External INT0
Timer 0
External INT1
Timer 1
Byte I²C-bus
Bit I²C-bus; note 1
VECTOR ADDRESS
000H
003H
00BH
013H
01BH
02BH
053H
Note
1. SAA5290, SAA5291, SAA5291A and SAA5491 only.
7.2.2 OFF-CHIP MEMORY
The SDIP52 version does not support the use of off-chip
program memory or off-chip data memory.
7.2.3 IDLE AND POWER-DOWN MODES
As Idle and Power-down modes are not supported, their
respective bits in PCON are not available.
7.2.4 UART FUNCTION
The 80C51 UART is not available. As a consequence the
SCON and SBUF SFRs are removed and the ES bit in the
IE SFR is unavailable.
7.3 Additional features
The following features are provided in addition to the
standard 80C51 features.
7.3.1 INTERRUPTS
The external INT1 interrupt is modified to generate an
interrupt on both the rising and falling edges of the INT1
pin, when EX1 bit is set. This facility allows for software
pulse width measurement for handling of a remote control.
7.3.2 BIT LEVEL I²C-BUS INTERFACE
For reasons of compatibility with SAA5290, the SAA5291,
SAA5291A and SAA5491 contain a bit level serial I/O
which supports the I²C-bus. P1.6/SCL and P1.7/SDA are
the serial I/O pins. These two pins meet the I²C-bus
specification “The I²C-bus and how to use it (including
specifications)” concerning the input levels and output
drive capability. Consequently, these two pins have an
open-drain output configuration. All the four following
modes of the I²C-bus are supported.
• Master transmitter
• Master receiver
• Slave transmitter
• Slave receiver.
Three SFRs support the function of the bit-level I²C-bus
hardware: S1INT, S1BIT and S1SCS and are enabled by
setting register bit TXT8.I²C SELECT to logic 0.
7.3.3 BYTE LEVEL I²C-BUS INTERFACE
The byte level serial I/O supports the I²C-bus protocol.
P1.6/SCL and P1.7/SDA are the serial I/O pins. These two
pins meet the I²C-bus specification concerning the input
levels and output drive capability. Consequently, these two
pins have an open-drain output configuration.
The byte level I²C-bus serial port is identical to the I²C-bus
serial port on the 8xC552. The operation of the subsystem
is described in detail in the 8xC552 data sheet found in
“80C51-Based 8-Bit Microcontrollers; Data Handbook
IC20”.
Four SFRs support the function of the byte level I²C-bus
hardware, they are S1CON, S1STA, S1DAT and S1ADR
and are enabled by setting register bit TXT8.I²C SELECT
to logic 1.
7.3.4 LED SUPPORT
Port pins P0.5 and P0.6 have a 10 mA current sinking
capability to enable LEDs to be driven directly.
1997 Jul 07
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