SAA5X9X Datasheet, PDF (8/68 Pages) NXP Semiconductors – Economy teletext and TV microcontrollers

Philips Semiconductors
Economy teletext and TV microcontrollers
Preliminary specification
SAA5x9x family
6.2 Pin description
Table 1 SDIP52 and QFP80 packages
SYMBOL
P2.0/TPWM
P2.1/PWM0
P2.2/PWM1
P2.3/PWM2
P2.4/PWM3
P2.5/PWM4
P2.6/PWM5
P2.7/PWM6
P3.0/ADC0
P3.1/ADC1
P3.2/ADC2
P3.3/ADC3
P3.4/PWM7
P3.5
P3.6
P3.7
V_SSD
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
V_SSA
CVBS0
CVBS1
BLACK
IREF
FRAME
V_SSD
COR
PIN
SDIP52 QFP80
1
77
2
78
3
79
4
80
5
9
6
8
7
1
8
2
9
3
10
5
11
6
12
7
30
44
−
46
−
48
−
22
13
12
14
14
15
15
16
16
17
20
18
21
19
24
20
25
21
26
22
27
23
28
24
29
25
30
26
31
27
36
28
37
29
38
DESCRIPTION
Port 2: 8-bit open-drain bidirectional port with alternative functions.
P2.0/TPWM is the output for the 14-bit high precision PWM.
P2.1/PWM0 to P2.7/PWM6 are the outputs for the 6-bit PWMs 0 to 6.
Port 3: 8-bit open-drain bidirectional port with alternative functions.
P3.0/ADC0 to P3.3/ADC3 are the inputs for the software ADC facility.
P3.4/PWM7 is the output for the 6-bit PWM7.
Digital ground.
Port 0: 8-bit open-drain bidirectional port.
P0.5 and P0.6 have 10 mA current sinking capability for direct drive of LEDs.
Analog ground.
Composite video inputs; a positive-going 1 V (peak-to-peak) input is required,
connected via a 100 nF capacitor.
Video black level storage input: this pin should be connected to V_SSA via a
100 nF capacitor.
Reference current input for analog circuits, connected to V_SSA via a 27 kΩ
resistor.
De-interlace output synchronised with the VSYNC pulse to produce a
non-interlaced display by adjustment of the vertical deflection circuits.
Internally connected; this pin should be connected to digital ground.
Open-drain, active LOW output which allows selective contrast reduction of
the TV picture to enhance a mixed mode display.
1997 Jul 07
8