SAA5X9X Datasheet, PDF (12/68 Pages) NXP Semiconductors – Economy teletext and TV microcontrollers

Philips Semiconductors
Economy teletext and TV microcontrollers
Preliminary specification
SAA5x9x family
7.3.6 14-BIT PWM DAC
One 14-bit DAC is available to allow direct control of
analog sections of the television. The 14-bit PWM is
controlled using Special Function Registers TDACL and
TDACH.
The output of the TPWM is a pulse of period 42.66 µs. The
7 most significant bits, TDACH.TD13
(MSB) to TDACH.TD8 and TDACL.TD7, alter the pulse
width between 0 and 42.33 µs, in much the same way as
in the 6-bit PWMs. The 7 least significant bits, TDACL.TD6
to TDACL.TD0 (LSB), extend certain pulses by a further
0.33 µs, e.g. if the 7 least significant bits are given the
value 01H, then 1 in 128 cycles is extended. If the 7 least
significant bits are given the value 02H, then
2 in 128 cycles is extended, and so forth.
The TPWM will not start to output a new value until after
writing a value to TDACH. Therefore, if the value is to be
changed, TDACL should be written to before TDACH.
7.3.6.1 TPWM High Byte Register (TDACH)
Table 5 TPWM High Byte Register (SFR address D3H)
7
6
5
4
3
2
1
0
PWE
−
TD13
TD12
TD11
TD10
TD9
TD8
Table 6 Description of TDACH bits
BIT
SYMBOL
DESCRIPTION
7
PWE If PWE is set to a logic 1, the TPWM is active and controls port line P2.0. If PWE is set
to a logic 0, the port pin is controlled by the corresponding bit in the port SFR.
6
−
Not used.
5
TD13 These 6-bits along with bit TD7 in the TDACL register control the pulse width period.
4
TD12
TD13 is the most significant bit.
3
TD11
2
TD10
1
TD9
0
TD8
7.3.6.2 TPWM Low Byte Register (TDACL)
Table 7 TPWM Low Byte Register (SFR address D2H)
7
6
5
4
3
2
1
0
TD7
TD6
TD5
TD4
TD3
TD2
TD1
TD0
Table 8 Description of TDACL bits
BIT
7
6 to 0
SYMBOL
DESCRIPTION
TD7
This bit is used with bits TD13 to TD8 in the TDACH register to control the pulse width
period.
TD6 to TD0 These 7-bits extend certain pulses by a further 0.33 µs.
1997 Jul 07
12