SAA5X9X Datasheet, PDF (46/68 Pages) NXP Semiconductors – Economy teletext and TV microcontrollers

Philips Semiconductors
Economy teletext and TV microcontrollers
Preliminary specification
SAA5x9x family
is achieved by modulating the vertical deflection current in
such a way that odd fields are shifted up and even fields
are shifted down on the screen so that lines 1 and 314,
2 and 315 etc. are overlaid. The FRAME output is
provided to facilitate this.
If the active edge of Vsync occurs in the first half of a TV
line this is an even field and the FRAME output should be
a logic 0 for this field. Similarly, if VSync is in the second
half of the line this is an odd field and FRAME should be a
logic1. The algorithm used to derive Frame is such that a
consistent output will be obtained no matter where the
VSync signal is relative to the HSync signal, even if VSync
occurs at the start and mid points of a line.
Setting the TXT0.DISABLE FRAME bit forces the FRAME
output to a logic 0. Setting the TXT0.AUTO FRAME bit
causes the FRAME output to be active when just text is
being displayed but to be forced to a logic 0 when any
video is being displayed. This allows the de-interlacing
function to take place with virtually no software
intervention.
Some TV architectures do not use the FRAME output but
accomplish the de-interlacing function in the vertical
deflection IC, under software control, by delaying the start
of the scan for one field by half a line, so that lines in this
field are moved up by one TV line. In such TVs, VSync
may occur in the first half of the line at the start of an odd
field and in the second half of the line at the start of an even
field. In order to obtain correct de-interlacing in these
circumstances, the TXT1.FIELD POLARITY must be set to
reverse the assumptions made by the vertical timing
circuits on the timing of VSync in each field. The start of the
display may be delayed by a line. The ‘Field Polarity’ bit
does not affect the FRAME output.
handbook, halfp_Ca_Vge_BS
TUNER/IF
VIDEO RGB
DECODING
SYNC ^{HSYNC, VSYNC}
CIRCUITS
CRT
DISPLAY
9.22 Display position
The position of the display relative to the HSync and
VSync inputs can be varied over a limited range to allow
for optimum TV set-up.
The horizontal position is controlled by the X0 and X1 bits
in TXT16. Table 23 gives the time from the active edge of
the HSync to the start of the display area for each setting
of X0 and X1.
Table 23 Display horizontal position
X1
X0
0
0
0
1
1
0
1
1
Hsync TO DISPLAY
(µs)
17.2
16.2
15.2
14.2
The line on which the display area starts depends on
whether the display is 625-line or 525-line and on the
setting of the Y0 to Y2 bits in TXT16. Table 24 gives the
first display line for each setting of Y0 to Y2, for both
625 and 525-line display.
On the other field, the display starts on the equivalent line.
Table 24 Display vertical position
FIRST LINE FOR DISPLAY
Y2
Y1
Y0
625-LINE 525-LINE
0
0
0
42
28
0
0
1
44
30
0
1
0
46
32
0
1
1
48
34
1
0
0
34
20
1
0
1
36
22
1
1
0
38
24
1
1
1
40
26
RGB, VDS
SAA5x9x FRAME
MGK464
Fig.14 Timing configuration.
1997 Jul 07
46