SAA5X9X Datasheet, PDF (38/68 Pages) NXP Semiconductors – Economy teletext and TV microcontrollers

Philips Semiconductors
Economy teletext and TV microcontrollers
Preliminary specification
SAA5x9x family
8.13 Fastext detection
When a packet 27, designation code 0 is detected,
whether or not it is acquired, the TXT13.FASTEXT bit is
set. If the device is receiving 525-line teletext, a packet
X/0/27/0 is required to set the flag. The flag can be reset
by writing a logic 0 into the SFR bit.
When a packet 8/30 is detected, or a packet 4/30 when the
device is receiving a 525-line transmission, the TXT13.Pkt
8/30 is set. The flag can be reset by writing a logic 0 into
the SFR bit.
8.14 Page clearing
When a page header is acquired for the first time after a
new page request or a page header is acquired with the
erase (C4) bit set the page memory is ‘cleared’ to spaces
before the rest of the page arrives.
When this occurs, the space code (20H) is written into
every location of rows 1 to 23 of the basic page memory,
row 1 of the extension packet memory and the row where
teletext packet 24 is written. This last row is either row 24
of the basic page memory, if the TXT0.X24 POSN bit is
set, or row 0 of the extension packet memory, if the bit is
not set. Page clearing takes place before the end of the TV
line in which the header arrived which initiated the page
clear. This means that the 1 field gap between the page
header and the rest of the page which is necessary for
many teletext decoders is not required.
The software can also initiate a page clear, by setting the
TXT9.CLEAR MEMORY bit. When it does so, every
location in the memory is cleared. The CLEAR MEMORY
bit is not latched so the software does not have to reset it
after it has been set.
Only one page can be cleared in a TV line so if the
software requests a page clear it will be carried out on the
next TV line on which the hardware does not force the
page to be cleared. A flag, TXT13.PAGE CLEARING, is
provided to indicate that a software requested page clear
is being carried out. The flag is set when a logic 1 is written
into the TXT9.CLEAR MEMORY bit and is reset when the
page clear has been completed.
At power-on and reset the whole of the page memory is
cleared and theTXT13.PAGE CLEARING bit will be set.
8.15 Full channel operation
If the TXT1.FULL FIELD bit is set the device will acquire
data transmitted on any TV line, not just during the vertical
blanking interval.
This allows the device to be used with teletext
transmissions occupying the entire TV channel and with
data extracted from different TV broadcast standards (e.g.:
MAC packet teletext).
8.16 Independent data services (SAA5291,
SAA5291A, SAA5491 only)
When the TXT8.IDS ENABLE bit is set, SAA5291
becomes a receiver for teletext ‘Independent Data
Services’. These services use teletext packet numbers 30
and 31 to transmit data from a central database to a large
number of distributed receivers.
Unlike normal teletext data, IDS data is not organised into
pages but into ‘data channels’.
There are 16 data channels, identified by the magazine
number and the LSB of the packet number (actually, the
second byte of the magazine and packet number group).
Data channel 0 is the familiar packet 8/30, used to transmit
broadcast related information.
The data channel to be captured by the device is selected
by writing to column 0 of the page request RAM.
Only IDS packets from the selected data channel are
captured and rows 0 to 23 of the basic page memory are
used to store the last 24 packets acquired. The first IDS
packet acquired after theTXT8.IDS ENABLE bit is set is
written into row 0, the next into row 1 and so on until 24
packets have been acquired. The internal packet counter
then rolls over and the 25th packet is written into row 0.
The hardware never initiates a page clear in IDS mode but
if the software initiates one the packet counter is reset to 0
after the memory is cleared.
The data bytes in the IDS packers are not error checked in
any way.
The software must keep track of which of the IDS packets
in the memory it has processed and detect newly arrived
packets. It can do this by writing a value which cannot be
produced by the 8/4 Hamming checker (such as FFH) into
column 0 of each row and detecting when it is over written.
The 24 packet buffer is sufficient to ensure that the device
will not be overwhelmed by IDS data sent in the vertical
blanking interval, but it may not be able to cope with full
channel IDS data.
IDS data is dealt with in the same way for both the
525 and 625-line teletext standards.
1997 Jul 07
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