SAA5X9X Datasheet, PDF (45/68 Pages) NXP Semiconductors – Economy teletext and TV microcontrollers

Philips Semiconductors
Economy teletext and TV microcontrollers
Preliminary specification
SAA5x9x family
Table 22 CLUT Address
CLUT ADDRESS
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
FULL INTENSITY EQUIVALENT
black foreground
red foreground
green Foreground
yellow foreground
blue foreground
magenta foreground
cyan foreground
white foreground
black background
red background
green background
yellow background
blue background
magenta background
cyan background
white background
9.17 Cursor
If the TXT7.CURSOR ON bit is set, a cursor is displayed.
The cursor operates by reversing the background and
foreground colours in the character position pointed to by
the active row and column bits in the TXT9 and TXT10
SFRs.
Setting the TXT9.CURSOR FREEZE bit, causes the
cursor to stay in its current position, no matter what
happens to the active row and column positions. This
means that the software can read data from the memory
(e.g. TOP table information) without affecting the position
of the cursor.
9.18 Other display features
Setting the TXT7.DOUBLE HEIGHT bit causes the normal
height of all display characters to be doubled and the
whole of the display area to be occupied by half of the
display rows. Characters normally displayed double height
will be displayed quadruple height when this bit is set.
Rows 12 to 24 can be enlarged, rather then rows 0 to 11,
by setting the TXT7.TOP/BOTTOM bit.
This feature can be used for either a user controlled
‘enlarge’ facility or to provide very large characters for
OSD.
The display of rows 0 to 23 can be disabled by setting the
TXT0.DISLAY STATUS ROW ONLY bit.
The Fastext prompt row (packet 24) can be displayed from
the extension packet memory by setting the
TXT0.DISPLAY X/24 bit. When this bit is set the data
displayed on display row 24 is taken from row 0 in the
extension packet memory.
When the display from extension packet block option is
enabled, the display will revert to row 24 of the basic page
memory if bit 3 of the link control byte in packet 27 is set.
9.19 Display timing
The display synchronises to the device’s HSync and
VSync inputs. A typical configuration is shown in Fig.14.
The HSync and VSync signals are derived from the signals
driving the deflection coils of the TV. The CVBS input is
only used to extract teletext from. Locking the display to
the signals from the scan circuits allows the device give a
stable display under almost all signal conditions.
The polarity of the input signals which the device is
expecting can be set using the TXT1.H polarity and
TXT1.V polarity bits. If the polarity bit is a logic 0, a positive
going signal is expected and if it is a logic 1, a negative
going signal is expected.
9.20 Horizontal timing
Every time an HSync pulse is received the display
resynchronizes to its leading edge. To get maximum
display stability, the HSync input must have fast edges,
free of noise to ensure that there is no uncertainty in the
timing of the signal to which the display synchronisation
circuits must lock.
The display area starts 17.2 µs into the line and lasts for
40 µs. The display area will be in the centre of the screen
if the HSync pulse is aligned with line flyback signal.
Therefore, it is better to derive HSync directly from the line
flyback or from an output of the line output transformer
than from, say, slicing the sandcastle signal as this would
introduce delays which would shift the display to the right.
9.21 Vertical timing
The vertical display timing also resynchronizes to every
sync pulse received. This means that the device can
produce a stable display on both 625 and 525-line
screens. Display starts on the 41st line of each field and
continues for 250 lines, or until the end of the field.
Normally, television displays are interlaced, i.e. only every
other TV line is displayed on each field. It is normal to
de-interlace teletext displays to prevent the displayed
characters flickering up and down. In many TV designs this
1997 Jul 07
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