NPIC6C4894_15 Datasheet, PDF (9/21 Pages) NXP Semiconductors – Power logic 12-bit shift register open-drain outputs

NXP Semiconductors
NPIC6C4894
Power logic 12-bit shift register; open-drain outputs
11. Dynamic characteristics
Table 7. Dynamic characteristics
At recommended operating conditions unless otherwise specified; Voltages are referenced to GND (ground = 0 V); For test
circuit, see Figure 15.
Symbol Parameter
Conditions
T_amb = 25 C
Unit
Min Typ Max
t_pd
propagation delay CP to QSn; see Figure 9
t_TLH
LOW to HIGH output QPn; see Figure 12
transition time
QSn; see Figure 9
[1]
-
5
- ns
-
60
- ns
-
6
- ns
t_THL
HIGH to LOW output QPn; see Figure 12
transition time
QSn; see Figure 9
-
18
- ns
-
6
- ns
t_PLZ
LOW to OFF-state CP, LE and OE to QPn; I_O = 75 mA;
propagation delay see Figure 10, Figure 11, Figure 12 and Figure 20
-
105
- ns
t_PZL
OFF-state to LOW CP, LE and OE to QPn; I_O = 75 mA;
propagation delay see Figure 10, Figure 11, Figure 12 and Figure 20
-
10
- ns
f_clk(max) maximum clock
frequency
CP; see Figure 9
[2] ₁₀
-
- MHz
t_su
set-up time
D to CP; see Figure 13
20
-
- ns
t_h
hold time
D to CP; see Figure 13
20
-
- ns
t_W
pulse width
CP, LE; see Figure 9 and Figure 11
40
-
- ns
t_rr
reverse recovery time I_O = 100 mA; dI/dt = 10 A/s; see Figure 14
[3][4]
-
120
- ns
t_a
reverse recovery
I_O = 100 mA; dI/dt = 10 A/s; see Figure 14
[3][4]
-
100
- ns
current rise time
[1] t_pd is the same as t_PLH and t_PHL.
[2] This is the maximum serial clock frequency assuming cascaded operation where serial data is passed from one stage to a second
stage. The clock period allows for CP → QSn propagation delay and setup time plus some timing margin.
[3] Technique should limit T_j  T_amb to 10 C maximum.
[4] These parameters are measured with voltage-sensing contacts separate from the current-carrying contacts.
NPIC6C4894
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 17 April 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
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