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| NPIC6C4894_15 Datasheet, PDF (12/21 Pages) NXP Semiconductors – Power logic 12-bit shift register open-drain outputs | |||
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NXP Semiconductors
NPIC6C4894
Power logic 12-bit shift register; open-drain outputs
9,
&3LQSXW
*1'
9,
'LQSXW
*1'
9
43QRXWSXW
92/
90
WVX
WK
90
WVX
WK
DDD
Measurement points are given in Table 8.
The shaded areas indicate when the input is permitted to change for predictable output performance.
VOL is the typical output voltage level that occurs with the output load.
Fig 13. Set-up and hold times
Table 8. Measurement points
Supply voltage
Input
VCC
VM
5V
0.5VCC
Output
VM
0.5VDS
VX
0.1VDS
VY
0.9VDS
.
43Q
'87
,2
W
W
W
P+
Â)
9
$
$
9
,2
GLGW $ÂV
RI,50
5*
9, *
GULYHU
È
,50
WD
WUU
DDD
(1) The open-drain QPn terminal under test is connected to testpoint K. All other terminals are connected together and connected
to testpoint A.
(2) The VI amplitude and RG are adjusted for dI/dt = 10 A/ïs. A VI double-pulse train is used to set IO = 0.1 A, where t1 = 10 ïs, t2
= 7 ïs and t3 = 3 ïs.
Fig 14. Test circuit and waveform for measuring reverse recovery current
NPIC6C4894
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 â 17 April 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
12 of 21
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