NPIC6C4894_15 Datasheet, PDF (11/21 Pages) NXP Semiconductors – Power logic 12-bit shift register open-drain outputs

NXP Semiconductors
NPIC6C4894
Power logic 12-bit shift register; open-drain outputs
9_,
&3LQSXW
*1'
9_,
/(LQSXW
*1'
9
43QRXWSXW
9_2/
9₀
9₀
W_:
W_3/=
9_;
W_3=/
9_<
DDD
Measurement points are given in Table 8.
V_OL is the typical output voltage level that occurs with the output load.
Fig 11. Latch enable (LE) to output (QPn) propagation delays and the latch enable pulse width
9_,
2(LQSXW
*1'
9
43QRXWSXW
9_2/
9₀
W_3/=
RXWSXWV
HQDEOHG
9_<
9_;
W_7/+
RXWSXWV
GLVDEOHG
W_3=/
9_<
9_;
W_7+/
RXWSXWV
HQDEOHG
DDD
Measurement points are given in Table 8.
V_OL is the typical output voltage level that occurs with the output load.
Fig 12. Output enable (OE) to output (QPn) and output transition time
NPIC6C4894
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 17 April 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
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