NPIC6C4894_15 Datasheet, PDF (5/21 Pages) NXP Semiconductors – Power logic 12-bit shift register open-drain outputs

NXP Semiconductors
NPIC6C4894
Power logic 12-bit shift register; open-drain outputs
7. Functional description
Table 3. Function table^[1]
At the positive clock edge, the information in the 10^th register stage is transferred to the 11^th register stage and the QS output
Control
Input
Parallel output
Serial output
CP
OE
LE
D
QP0
QPn
QS1^[2]
QS2^[3]

L
X
X
Z
Z
Q10S
no change

L
X
X
Z
Z
no change Q11S

H
L
X
no change no change Q10S
no change

H
H
L
Z
QPn1
Q10S
no change

H
H
H
L
QPn1
Q10S
no change

H
H
H
no change no change no change Q11S
[1] H = HIGH voltage level; L = LOW voltage level; X = don’t care;  = LOW-to-HIGH clock transition;  = HIGH-to-LOW clock transition;
Z = high-impedance OFF-state.
[2] Q10S = the data in register stage 10 before the LOW to HIGH clock transition.
[3] Q11S = the data in register stage 11 before the HIGH to LOW clock transition.
&3LQSXW
'LQSXW
/(LQSXW
2(LQSXW
LQWHUQDO46
))
43RXWSXW
LQWHUQDO46
))
43RXWSXW
VHULDO46
RXWSXW
VHULDO46
RXWSXW
Fig 7. Timing diagram
DDD
NPIC6C4894
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 17 April 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
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