83C751 Datasheet, PDF (9/24 Pages) NXP Semiconductors – 80C51 8-bit microcontroller family 2K/64 OTP/ROM, I2C, low pin count

Philips Semiconductors
80C51 8-bit microcontroller family
2K/64 OTP/ROM, I²C, low pin count
Product specification
83C751/87C751
OSCILLATOR CHARACTERISTICS
X1 and X2 are the input and output, respectively, of an inverting
amplifier which can be configured for use as an on-chip oscillator.
To drive the device from an external clock source, X1 should be
driven while X2 is left unconnected. There are no requirements on
the duty cycle of the external clock signal, because the input to the
internal clock circuitry is through a divide-by-two flip-flop. However,
minimum and maximum high and low times specified in the data
sheet must be observed.
RESET
A reset is accomplished by holding the RST pin high for at least two
machine cycles (24 oscillator periods), while the oscillator is running.
To insure a good power-up reset, the RST pin must be high long
enough to allow the oscillator time to start up (normally a few
milliseconds) plus two machine cycles. At power-up, the voltage on
V_CC and RST must come up at the same time for a proper start-up.
IDLE MODE
In idle mode, the CPU puts itself to sleep while all of the on-chip
peripherals stay active. The instruction to invoke the idle mode is the
last instruction executed in the normal operating mode before the
idle mode is activated. The CPU contents, the on-chip RAM, and all
of the special function registers remain intact during this mode. The
idle mode can be terminated either by any enabled interrupt (at
which time the process is picked up at the interrupt service routine
and continued), or by a hardware reset which starts the processor in
the same manner as a power-on reset.
POWER-DOWN MODE
In the power-down mode, the oscillator is stopped and the
instruction to invoke power-down is the last instruction executed.
Only the contents of the on-chip RAM are preserved. A hardware
reset is the only way to terminate the power-down mode. the control
bits for the reduced power modes are in the special function register
PCON.
Table 1. External Pin Status During Idle and
Power-Down Modes
MODE
Port 0
Port 1
Port 2
Idle
Power-down
Data
Data
Data
Data
Data
Data
DIFFERENCES BETWEEN THE 8XC751 AND THE
80C51
Memory Organization
The central processing unit (CPU) manipulates operands in two
address spaces as shown in Figure 3. The part’s internal memory
space consists of 2k bytes of program memory, and 64 bytes of data
RAM overlapped with the 128-byte special function register area.
The differences from the 80C51 are in RAM size (64 bytes vs. 128
bytes), in external RAM access (not available on the 83C751), in
internal ROM size (2k bytes vs. 4k bytes), and in external program
memory expansion (not available on the 83C751). The 128-byte
special function register (SFR) space is accessed as on the 80C51
with some of the registers having been changed to reflect changes
in the 83C751 peripheral functions. The stack may be located
anywhere in internal RAM by loading the 8-bit stack pointer (SP). It
should be noted that stack depth is limited to 64 bytes, the amount
of available RAM. A reset loads the stack pointer with 07 (which is
pre-incremented on a PUSH instruction).
(FFH) 255
(80H) 128
(3FH) 63
Special
Function
Registers
Internal Data
RAM
(00H) 0
Figure 3. Memory Map
SU00299
Program Memory
On the 8XC751, program memory is 2048 bytes long and is not
externally expandable, so the 80C51 instructions MOVX, LJMP, and
LCALL are not implemented. The only fixed locations in program
memory are the addresses at which execution is taken up in
response to reset and interrupts, which are as follows:
Program Memory
Event
Address
Reset
000
External INT0
003
Counter/timer 0
00B
External INT1
013
Timer I
01B
I²C serial
023
Counter/Timer Subsystem
The 8XC751 has one counter/timer called timer/counter 0. Its
operation is similar to mode 2 operation on the 80C51, but is
extended to 16 bits with 16 bits of autoload. The controls for this
counter are centralized in a single register called TCON.
A watchdog timer, called Timer I, is for use with the I²C subsystem.
In I²C applications, this timer is dedicated to time-generation and
bus monitoring of the I²C. In non-I²C applications, it is available for
use as a fixed time-base.
Counter Timer – Special Function Register
The counter/timer has only one mode of operation, so the TMOD
SFR is not used. There is also only one counter/timer, so there is no
need for the TL1 and TH1 SFRs found on the 80C51. These have
been replaced on the 83C751 by RTL and RTH, the counter/timer
reload registers. Table 3 shows the special function registers, their
locations, and reset values.
Interrupt Subsystem – Fixed Priority
The IP register and the 2-level interrupt system of the 80C51 are
eliminated. Simultaneous interrupt conditions are resolved by a
single-level, fixed priority as follows:
Highest priority:
Lowest priority:
Pin INT0
Counter/timer flag 0
Pin INT1
Timer I
Serial I²C
1998 May 01
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