83C751 Datasheet, PDF (14/24 Pages) NXP Semiconductors – 80C51 8-bit microcontroller family 2K/64 OTP/ROM, I2C, low pin count

Philips Semiconductors
80C51 8-bit microcontroller family
2K/64 OTP/ROM, I²C, low pin count
Product specification
83C751/87C751
Checking ATN and DRDY
When a program detects ATN = 1, it should next check DRDY. If
DRDY = 1, then if it receives the last bit, it should capture the data
from RDAT (in I2DAT or I2CON). Next, if the next bit is to be sent, it
should be written to I2DAT. One way or another, it should clear
DRDY and then return to monitoring ATN. Note that if any of ARL,
STR, or STP is set, clearing DRDY will not release SCL to high, so
that the I²C will not go on to the next bit. If a program detects
ATN = 1, and DRDY = 0, it should go on to examine ARL, STR, and
STP.
ARL
STR
STP
“Arbitration Loss” is 1 when transmit Active was set, but
this 83C751 lost arbitration to another transmitter.
Transmit Active is cleared when ARL is 1. There are four
separate cases in which ARL is set.
1. If the program sent a 1 or repeated start, but another
device sent a 0, or a stop, so that SDA is 0 at the
rising edge of SCL. (If the other device sent a stop, the
setting of ARL will be followed shortly by STP being
set.)
2. If the program sent a 1, but another device sent a
repeated start, and it drove SDA low before the
83C751 could drive SCL low. (This type of ARL is
always accompanied by STR = 1.)
3. In master mode, if the program sent a repeated start,
but another device sent a 1, and it drove SCL low
before this 83C751 could drive SDA low.
4. In master mode, if the program sent stop, but it could
not be sent because another device sent a 0.
“STaRt” is set to a 1 when an I²C start condition is
detected at a non-idle slave or at a master. (STR is not set
when an idle slave becomes active due to a start bit; the
slave has nothing useful to do until the rising edge of SCL
sets DRDY.)
“SToP” is set to 1 when an I²C stop condition is detected
at a non-idle slave or at a master. (STP is not set for a
stop condition at an idle slave.)
MASTER “MASTER” is 1 if this 83C751 is currently a master on the
I²C. MASTER is set when MASTRQ is 1 and the bus is
not busy (i.e., if a start bit hasn’t been received since reset
or a “Timer I” time-out, or if a stop has been received since
the last start). MASTER is cleared when ARL is set, or
after the software writes MASTRQ = 0 and then XSTP = 1.
Writing I2CON
Typically, for each bit in an I²C message, a service routine waits for
ATN = 1. Based on DRDY, ARL, STR, and STP, and on the current
bit position in the message, it may then write I2CON with one or
more of the following bits, or it may read or write the I2DAT register.
CXA
Writing a 1 to “Clear Xmit Active” clears the Transmit
Active state. (Reading the I2DAT register also does this.)
Regarding Transmit Active
Transmit Active is set by writing the I2DAT register, or by writing
I2CON with XSTR = 1 or XSTP = 1. The I²C interface will only drive
the SDA line low when Transmit Active is set, and the ARL bit will
only be set to 1 when Transmit Active is set. Transmit Active is
cleared by reading the I2DAT register, or by writing I2CON with
CXA = 1. Transmit Active is automatically cleared when ARL is 1.
IDLE
Writing 1 to “IDLE” causes a slave’s I²C hardware to
ignore the I²C until the next start condition (but if MASTRQ
is 1, then a stop condition will make the 83C751 into a
master).
CDR
Writing a 1 to “Clear Data Ready” clears DRDY. (Reading
or writing the I2DAT register also does this.)
CARL Writing a 1 to “Clear Arbitration Loss” clears the ARL bit.
CSTR Writing a 1 to “Clear STaRt” clears the STR bit.
CSTP
XSTR
XSTP
Writing a 1 to “Clear SToP” clears the STP bit. Note that if
one or more of DRDY, ARL, STR, or STP is 1, the low time
of SCL is stretched until the service routine responds by
clearing them.
Writing 1s to “Xmit repeated STaRt” and CDR tells the I²C
hardware to send a repeated start condition. This should
only be at a master. Note that XSTR need not and should
not be used to send an “initial” (nonrepeated) start; it is
sent automatically by the I²C hardware. Writing XSTR = 1
includes the effect of writing I2DAT with XDAT = 1; it sets
Transmit Active and releases SDA to high during the SCL
low time. After SCL goes high, the I²C hardware waits for
the suitable minimum time and then drives SDA low to
make the start condition.
Writing 1s to “Xmit SToP” and CDR tells the I²C hardware
to send a stop condition. This should only be done at a
master. If there are no more messages to initiate, the
service routine should clear the MASTRQ bit in I2CFG to 0
before writing XSTP with 1. Writing XSTP = 1 includes the
effect of writing I2DAT with XDAT = 0; it sets Transmit
Active and drives SDA low during the SCL low time. After
SCL goes high, the I²C hardware waits for the suitable
minimum time and then releases SDA to high to make the
stop condition.
NOTE: Because of the manner in which register bit addressing is
implemented in the 80C51 family, the I2CON register should never be
altered by use of the SETB, CLR, CPL, MOV (bit), or JBC
instructions. This is due to the fact that read and write functions of this
register are different. Testing of I2CON bits via the JB and JNB
instructions is supported.
1998 May 01
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