83C751 Datasheet, PDF (16/24 Pages) NXP Semiconductors – 80C51 8-bit microcontroller family 2K/64 OTP/ROM, I2C, low pin count

Philips Semiconductors
80C51 8-bit microcontroller family
2K/64 OTP/ROM, I²C, low pin count
Product specification
83C751/87C751
Table 4. Interaction of TIRUN with SLAVEN, MASTRQ, and MASTER
SLAVEN,
MASTRQ,
MASTER
All 0
All 0
Any or all 1
Any or all 1
TIRUN
OPERATING MODE
0
The I²C interface is disabled. Timer I is cleared and does not run. This is the state assumed after a reset. If an I²C
application wants to ignore the I²C at certain times, it should write SLAVEN, MASTRQ, and TIRUN all to zero.
1
The I²C interface is disabled. Timer I operates as a free-running time base. Use this mode only in non-I²C
applications.
0
The I²C interface is enabled. The 3 low-order bits of Timer I run for min-time generation, but the hi-order bits do
not, so that there is no checking for I²C being “hung.” This configuration can be used for very slow I²C operation.
1
The I²C interface is enabled. Timer I runs during frames on the I²C, and is cleared by transitions on SCL, and by
Start and Stop conditions. This is the normal state for I²C operation.
Table 5. CT1, CT0 Values
CT1, CT0
10
01
00
11
OSC/12 COUNT
7
6
5
4
f_OSC MAX
16.8MHz
14.4MHz
12.0MHz
9.6MHz
TIMEOUT PERIOD
1023 cycles
1022 cycles
1021 cycles
1020 cycles
I²C Register I2STA
READ ONLY
7
6
5
4
3
2
1
–
IDLE XDATA XACTV MAKSTR MAKSTP XSTR
0
XSTP
MSB
LSB
This register is read only and reflects the internal status of the I²C
hardware. IDLE, XSTR, and XSTP reflect the status of the like
named bits in the I2CON register.
XDATA The content of the transmitter buffer.
XACTV Transmitter active.
MAKSTR This bit is high while the hardware is effecting a start
condition.
MAKSTP This bit is high while the hardware is effecting a stop
condition.
XSTR
This bit is active while the hardware is effecting a
repeated start condition.
XSTP
This bit is active while the hardware is effecting a
repeated stop condition.
Interrupts
The interrupt structure is a five-source, one-level interrupt system.
Interrupt sources common to the 80C51 are the external interrupts
(INT0, INT1) and the timer/counter interrupt (ET0). The I²C interrupt
(EI2) and Timer I interrupt (ETI) are the other two interrupt sources.
The interrupt sources are listed below in their order of polling
sequence priority.
Upon interrupt or reset the program counter is loaded with specific
values for the appropriate interrupt service routine in program
memory. These values are:
Program Memory
Event
Address
Reset
000
INT0
003
Counter/Timer 0
00B
INT1
013
Timer I
01B
I²C
023
Priority
Highest
Lowest
The interrupt enable register (IE) is used to individually enable or
disable the five sources. Bit EA in the interrupt enable register can
be used to globally enable or disable all interrupt sources. The
interrupt enable register is described below. All other interrupt details
are based on the 80C51 interrupt architecture.
Interrupt Enable Register
7
6
5
4
3
2
1
0
EA
X
X
EI2
ETI
EX1
ET0
EX0
Symbol Position Function
EA IE.7
Disables all interrupts. If EA = 0, no interrupt
will be acknowledged. If EA = 1, each interrupt
source is individually enabled or disabled by
setting or clearing its enable bit
–
IE.6
Reserved
–
IE.5
Reserved
EI2
IE.4
Enables or disables the I²C interrupt.
If EI2 = 0, the I²C interrupt is disabled
ETI
IE.3
Enables or disables the Timer I overflow
interrupt. If ETI = 0, the Timer I interrupt is
disabled.
EX1
IE.2
Enables or disables external interrupt 1.
If EX1 = 0, external interrupt 1 is disabled.
ET0
IE.1
Enables or disables the Timer 0 overflow
interrupt. If ET0 = 0, theTimer 0 interrupt is
disabled.
EX0
IE.0
Enables or disables external interrupt 0.
If EX0 = 0, external interrupt 0 is disabled.
1998 May 01
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