83C751 Datasheet, PDF (12/24 Pages) NXP Semiconductors – 80C51 8-bit microcontroller family 2K/64 OTP/ROM, I2C, low pin count

Philips Semiconductors
80C51 8-bit microcontroller family
2K/64 OTP/ROM, I²C, low pin count
Product specification
83C751/87C751
I/O Port Structure
The 8XC751 has two 8-bit ports (ports 1 and 3) and one 3-bit port
(port 0). All three ports on the 8XC751 are bidirectional. Each
consists of a latch (special function register P0, P1, P3), an output
driver, and an input buffer. Three port 1 pins and two port 0 pins are
multifunctional. In addition to being port pins, these pins serve the
function of special features as follows:
Port PinAlternate Function
P0.0 I²C clock (SCL)
P0.1 I²C data (SDA)
P1.5 INT0 (external interrupt 0 input)
P1.6 INT1 (external interrupt 1 input)
P1.7 T0 (timer 0 external input)
Ports 1 and 3 are identical in structure to the same ports on the
80C51. The structure of port 0 on the 8XC751 is similar to that of the
80C51 but does not include address/data input and output circuitry.
As on the 80C51, ports 1 and 3 are quasi-bidirectional while port 0 is
bidirectional with no internal pullups.
Timer/Counter
The 8XC751 has two timers: a 16-bit timer/counter and a 10-bit
fixed-rate timer. The 16-bit timer/counter’s operation is similar to
mode 2 operation on the 80C51, but is extended to 16 bits. The
timer/counter is clocked by either 1/12 the oscillator frequency or by
transitions on the T0 pin. The C/T pin in special function register
TCON selects between these two modes. When the TCON TR bit is
set, the timer/counter is enabled. Register pair TH and TL are
incremented by the clock source. When the register pair overflows,
the register pair is reloaded with the values in registers RTH and
RTL. The value in the reload registers is left unchanged. See the
83C751 counter/timer block diagram in Figure 4. The TF bit in
special function register TCON is set on counter overflow and, if the
interrupt is enabled, will generate an interrupt.
TCON Register
MSB
LSB
GATE C/T
TF
TR
IE0
IT0
IE1
IT1
GATE 1
0
C/T 1
0
TF 1
0
TR 1
0
IE0 1
IT0 1
0
IE1 1
IT1 1
0
– Timer/counter is enabled only when INT0 pin is
high, and TR is 1.
– Timer/counter is enabled when TR is 1.
– Counter/timer operation from T0 pin.
– Timer operation from internal clock.
– Set on overflow of TH.
– Cleared when processor vectors to interrupt routine
and by reset.
– Timer/counter enabled.
– Timer/counter disabled.
– Edge detected in INT0.
– INT0 is edge triggered.
– INT0 is level sensitive.
– Edge detected on INT1.
– INT1 is edge triggered.
– INT1 is level sensitive.
These flags are functionally identical to the corresponding 80C51
flags, except that there is only one timer on the 83C751 and the
flags are therefore combined into one register.
Note that the positions of the IE0/IT0 and IE1/IT1 bits are
transposed from the positions used in the standard 80C51 TCON
register.
Timer I is used to control the timing of the I²C bus and also to detect
a “bus locked” condition, by causing an interrupt when nothing
happens on the I²C bus for an inordinately long period of time while
a transmission is in progress. If the interrupt does not occur, the
program can attempt to correct the fault and allow the last I²C
transmission to be repeated.
The I²C watchdog timer, timer I, is also available as a
general-purpose fixed-rate timer when the I²C interface is not being
used. A clock rate of 1/12 the oscillator frequency forms the input to
the timer. Timer I has a timeout interval of 1024 machine cycles
when used as a fixed-rate timer.
OSC
T0 Pin
TR
Gate
INT0 Pin
÷ 12
C/T = 0
C/T = 1
TL
TH
TF
Reload
RTL
RTH
Figure 4. 83C751 Counter/Timer Block Diagram
Int.
SU00300
1998 May 01
12