83C751 Datasheet, PDF (13/24 Pages) NXP Semiconductors – 80C51 8-bit microcontroller family 2K/64 OTP/ROM, I2C, low pin count

Philips Semiconductors
80C51 8-bit microcontroller family
2K/64 OTP/ROM, I²C, low pin count
Product specification
83C751/87C751
I²C Serial Interface
The I²C bus uses two wires (SDA and SCL) to transfer information
between devices connected to the bus. The main features of the bus
are:
• Bidirectional data transfer between masters and slaves
• Serial addressing of slaves (no added wiring)
• Acknowledgment after each transferred byte
• Multimaster bus
• Arbitration between simultaneously transmitting masters without
corruption of serial data on bus
• The 82B715 extends communication distance to 100 feet (30M).
A large family of I²C compatible ICs is available. See the I²C section
of this manual for more details on the bus and available ICs.
The 83C751 I²C subsystem includes hardware to simplify the
software required to drive the I²C bus. The hardware is a single bit
interface which in addition to including the necessary arbitration and
framing error checks, includes clock stretching and a bus timeout
timer. The interface is synchronized to software either through polled
loops or interrupts. Refer to the application note AN422, in
Section 4, entitled “Using the 8XC751 Microcontroller as an I²C Bus
Master” for additional discussion of the 83C751 I²C interface and
sample driver routines.
Six time spans are important in I²C operation and are insured by
timer I:
• The MINIMUM HIGH time for SCL when this device is the master.
• The MINIMUM LOW time for SCL when this device is a master.
This is not very important for a single-bit hardware interface like
this one, because the SCL low time is stretched until the software
responds to the I²C flags. The software response time normally
meets or exceeds the MIN LO time. In cases where the software
responds within MIN HI + MIN LO) time, timer I will ensure that
the minimum time is met.
• The MINIMUM SCL HIGH TO SDA HIGH time in a stop condition.
• The MINIMUM SDA HIGH TO SDA LOW time between I²C stop
and start conditions (4.7µs, see spec.).
• The MINIMUM SDA LOW TO SCL LOW time in a start condition.
• The MAXIMUM SCL CHANGE time while an I²C frame is in
progress. A frame is in progress between a start condition and the
following stop condition. This time span serves to detect a lack of
software response on this 8XC751 as well as external I²C
problems. SCL “stuck low” indicates a faulty master or slave. SCL
“stuck high” may mean a faulty device, or that noise induced onto
the I²C bus caused all masters to withdraw from I²C arbitration.
The first five of these times are 4.7µs (see I²C specification) and are
covered by the low order three bits of timer I. Timer I is clocked by
the 8XC751 oscillator, which can vary in frequency from 0.5 to
16MHz. Timer I can be preloaded with one of four values to optimize
timing for different oscillator frequencies. At lower frequencies,
software response time is increased and will degrade maximum
performance of the I²C bus. See special function register I2CFG
description for prescale values (CT0, CT1).
The MAXIMUM SCL CHANGE time is important, but its exact span
is not critical. The complete 10 bits of timer I are used to count out
the maximum time. When I²C operation is enabled, this counter is
cleared by transitions on the SCL pin. The timer does not run
between I²C frames (i.e., whenever reset or stop occurred more
recently than the last start). When this counter is running, it will carry
out after 1020 to 1023 machine cycles have elapsed since a change
on SCL. A carry out causes a hardware reset of the 83C751 I²C
interface and generates an interrupt if the timer I interrupt is
enabled. In cases where the bus hangup is due to a lack of software
response by this 83C751, the reset releases SCL and allows I²C
operation among other devices to continue.
I²C Interrupts
If I²C interrupts are enabled (EA and EI2 are both set to 1), an I²C
interrupt will occur whenever the ATN flag is set by a start, stop,
arbitration loss, or data ready condition (refer to the description of
ATN following). In practice, it is not efficient to operate the I²C
interface in this fashion because the I²C interrupt service routine
would somehow have to distinguish between hundreds of possible
conditions. Also, since I²C can operate at a fairly high rate, the
software may execute faster if the code simply waits for the I²C
interface.
Typically, the I²C interrupt should only be used to indicate a start
condition at an idle slave device, or a stop condition at an idle master
device (if it is waiting to use the I²C bus). This is accomplished by
enabling the I²C interrupt only during the aforementioned conditions.
I²C Register I2CON
7
6
5
4
3
2
1
0
Read RDAT ATN DRDY ARL STR STP MASTER
–
Write CXA IDLE CDR CARL CSTR CSTP XSTR XSTP
Reading I2CON
RDAT
The data from SDA is captured into “Receive DATa”
whenever a rising edge occurs on SCL. RDAT is also
available (with seven low-order zeros) in the I2DAT
register. The difference between reading it here and there
is that reading I2DAT clears DRDY, allowing the I²C to
proceed on to another bit. Typically, the first seven bits of a
received byte are read from I2DAT, while the 8th is read
here. Then I2DAT can be written to send the Ack bit and
clear DRDY.
ATN “ATteNtion” is 1 when one or more of DRDY, ARL, STR, or
STP is 1. Thus, ATN comprises a single bit that can be
tested to release the I²C service routine from a “wait loop.”
DRDY
“Data ReaDY” (and thus ATN) is set when a rising edge
occurs on SCL, except at idle slave. DRDY is cleared by
writing CDR = 1, or by writing or reading the I2DAT
register. The following low period on SCL is stretched until
the program responds by clearing DRDY.
1998 May 01
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