83C751 Datasheet, PDF (15/24 Pages) NXP Semiconductors – 80C51 8-bit microcontroller family 2K/64 OTP/ROM, I2C, low pin count

Philips Semiconductors
80C51 8-bit microcontroller family
2K/64 OTP/ROM, I²C, low pin count
Product specification
83C751/87C751
I²C Register I2DAT
7
6
5
4
3
2
1
0
Read RDAT
0
0
0
0
0
0
0
Write XDAT
X
X
X
X
X
X
X
RDAT
XDAT
“Receive DATa” is captured from SDA every rising edge of
SCL. Reading I2DAT also clears DRDY and the Transmit
Active state.
“Xmit Data” sets the data for the next bit. Writing I2DAT
also clears DRDY and sets the Transmit Active state.
Regarding Software Response Time
Because the 83C751 can run at 16MHz, and because the I²C
interface is optimized for high-speed operation, it is quite likely that
an I²C service routine will sometimes respond to DRDY (which is set
at a rising edge of SCL) and write I2DAT before SCL has gone low
again. If XDAT were applied directly to SDA, this situation would
produce an I²C protocol violation. The programmer need not worry
about this possibility because XDAT is applied to SDA only when
SCL is low.
Conversely, a program that includes an I²C service routine may take
a long time to respond to DRDY. Typically, an I²C routine operates
on a flag-polling basis during a message, with interrupts from other
peripheral functions enabled. If an interrupt occurs, it will delay the
response of the I²C service routine. The programmer need not worry
about this very much either, because the I²C hardware stretches the
SCL low time until the service routine responds. The only constraint
on the response is that it must not exceed the Timer I time-out,
which is at least 765 microseconds.
I²C Register I2CFG
7
6
5
4
3
2
1
0
Read SLAVEN MASTRQ
0
TIRUN –
– CT1 CT0
Write SLAVEN MASTRQ CLRTI TIRUN –
– CT1 CT0
SLAVEN Writing a 1 to “SLAVe ENable” enables the slave functions
of the I²C subsystem. If SLAVEN and MASTRQ are 0, the
I²C hardware is disabled. This bit is cleared to 0 by reset
and by an I²C time-out.
MASTRQ Writing a 1 to “MASTRQ” requests mastership of the I²C.
If a frame from another master is in progress when this
bit is changed from 0 to 1, action is delayed until a stop
condition is detected. Then, or immediately if a frame is
not in progress, a start condition is sent and DRDY is set
(thus making ATN 1 and generating an I²C interrupt).
When a master wishes to release mastership status of
the I²C, it writes a 1 to XSTP in I2CON. MASTRQ is
cleared by reset and by an I²C time-out.
CLRTI Writing a 1 to this bit clears the Timer I interrupt flag. This
bit position always reads as a 0.
TIRUN
Writing a 1 to this bit lets Timer I run; a zero stops and
clears it. Together with SLAVEN, MASTRQ, and
MASTER, this bit determines operational modes as
shown in Table 4.
CT1,0
These two bits are programmed as a function of the OSC
rate, to optimize the MIN HI and LO time of SCL when
this 83C751 is a master on the I²C. The time value
determined by these bits controls both of these
parameters, and also the timing for stop and start
conditions. These bits are cleared to 00 by reset.
Values to be used in the CT1 and CT0 bits are shown in Table 5. To
allow the I²C bus to run at the maximum rate for a particular
oscillator frequency, compare the actual oscillator rate to the f_OSC
max column in the table. The value for CT1 and CT0 is found in the
first line of the table where f_OSC max is greater than or equal to the
actual frequency.
The table also shows the osc/12 count for various settings of
CT1/CT0. This allows calculation of the actual minimum high and
low times for SCL as follows:
SCL min high/low time (in microseconds) = 12 * count / osc (in MHz)
For instance, at a 16MHz frequency, with CT1/CT0 set to 10, the
minimum SCL high and low times will be 5.25µs.
The table also shows the Timer I timeout period (given in machine
cycles) for each CT1/CT0 combination. The timeout period varies
because of the way in which minimum SCL high and low times are
measured. When the I²C interface is operating, Timer I is preloaded
at every SCL transition with a value dependent upon CT1/CT0. The
preload value is chosen such that a minimum SCL high or low time
has elapsed when Timer I reaches a count of 008 (the actual value
preloaded into Timer I is 8 minus the osc/12 count).
1998 May 01
15