80CL31 Datasheet, PDF (7/40 Pages) NXP Semiconductors – Low-voltage single-chip 8-bit microcontrollers

Philips Semiconductors
Low-voltage single-chip 8-bit microcontrollers
Product specification
80CL31/80CL51
7FH
2FH
BIT-ADDRESSABLESPACE
(BIT ADDRESSES 0-7F)
20H
R7
1FH
I
I
R0
18H
R7
17H
I
I
4 BANKS OF 8 REGISTERS
R0
10H
(R0-R)
R7
0FH
I
I
R0
08H
R7
07H
I
I
R0
0
Figure 1. The Lower 128 Bytes of Internal RAM
The first three methods can be used for addressing destination
operands. Most instructions have a “destination/source” filed that
specifies data type, addressing methods and operands involved. For
operations other than MOVs, the destination operand is also a
source operand.
Access to memory addressing is as follows:
– Registers in one of the four register banks through register,
direct or indirect.
– Internal RAM (128 bytes) through direct or register-indirect.
– Special Function Register through Direct.
– External data memory through Register-lndirect
– Program memory look-up tables through Base-Register-Plus
Index-Register-Indirect.
1.2 I/O Facilities
1.2.1 Ports
The 80CL51 has 32 I/O lines treated as 32 individually addressable
bits or as four parallel 8- bit addressable ports. Port 0, 1, 2 and 3
perform the following alternate functions:
Port 0:
provides the multiplexed low-order address and data bus
for expanding the device with standard memories and
peripherals.
Port 1: provides the inputs for the external interrupts INT2/lNT9.
Port 2: provides the high-order address when expanding the
device with external program or data memory.
Port 3:
pins can be configured individually to provide:
(1) external interrupt request inputs
(2) counter input
(3) control signals to read and write to external memories
(4) UART input and output
To enable a Port 3 pin alternate function, the Port 3 bit latch in its
SFR must contain a logic 1.
Each port consists of a latch (Special Function Registers P0 to P3),
an output driver and an input buffer. Ports 1,2,3 have internal pull
ups. Figure 3(a) shows that the strong transistor p1 is turned on for
only 2 oscillator periods after a 0-to-1 transition in the port latch.
When on, it turns on p3 (a weak pull up) through the inverter. This
inverter and p3 form a latch which hold the 1. In Port 0 the pull up p1
is only on when emitting 1s for external memory access. Writing a 1
to a Port 0 bit latch leaves both output transistors switched off so the
pin can be used as a high-impedance input.
1.2.2 Port Options
The pins of port 1, port 2, and port 3 may be individually configured
with one of the following options (see Figure 3):
Option 1: Standard Port; quasi-bidirectional I/O with pull up. The
strong booster pull up p1 is turned on for two oscillator
periods after a 0-to-1 transition in the port latch (see
Figure 3(a)).
Option 2: Open drain; quasi-bidirectional I/O with n-channel open
drain output. Use as an output requires the connection of
an external pull up resistor (see Figure 3(c)).
Option 3: Push-Pull; output with drive capability in both polarities.
Under this option, pins can only be used as outputs. See
Figure 3(b).
January 1995
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